Apparatus and method for enabling elements of a phase locked loop

• US 6,185,411 B1
• Filed: 08/29/1997
• Issued: 02/06/2001
• Est. Priority Date: 11/09/1993
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Kosiec, Jeannie Han, Gillig, Steven Frederick
• Primary Examiner(s): Urban, Edward F.
• Application Number:
  US08/939,157
• Time in Patent Office: 1,257 Days
• Field of Search: 455/38.3, 455/180.3, 455/183.2, 455/260, 455/264, 455/265, 455/76, 455/343, 331/10, 331/14, 331/17, 331/19, 331/25, 331/9, 375/376
• US Class Current: 455/260
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

An apparatus and method enables elements of a phase locked loop (PLL) (300). The PLL 300 includes a plurality of elements (202, 203, 204, 205). Each element produces an output signal (207, 208, 209, 116 or 117). Each element has a response time (t3−t2) defined by the difference in time between a first time (t2) at which the element is enabled and a second time (t3), occurring after the first time (t2), at which the output signal of the element reaches a steady state condition. A voltage controlled oscillator (204) of the plurality of elements, having a first response time (t3−t2) is enabled at the first time (t2) responsive to a first control signal (302). A loop divider (205) of the plurality of elements, having a second response time less than the first response time (t3−t2), is enabled responsive to the first response time (t3−t2) and a second control signal (303). The present invention advantageously provides fast lock time for the PLL (300).

Claims

1. In a phase locked loop (PLL) having a plurality of elements including a first element and a second element, each of the first element and the second element having an input terminal and an output terminal, the output terminal of the first element being coupled to the input terminal of the second element and the output terminal of the second element being coupled to the input terminal of the first element to form a feedback signal arrangement in the PLL, each element having a response time defined by a difference in time between a first time at which the element is enabled and a second time, occurring after the first time, at which the output signal of the element reaches a steady state condition, the PLL having a response time defined by a difference in time between a time when a disabled element of the plurality of elements is enabled and a time when an output frequency signal of the PLL reaches a steady state condition, a method for minimizing the response time of the PLL while minimizing power consumption of the PLL comprising the steps of:

enabling the first element, having a first response time, responsive to a first control signal;

monitoring, directly from the first element, an indication of when an output signal of the first element has substantially reached its steady state frequency condition;

controlling a second control signal responsive to the monitored indication; and

enabling the second element, having a second response time less than the first response time, responsive to the second control signal.

2. A method according to claim 1 wherein the first element is a voltage controlled oscillator.

3. A method according to claim 1 wherein the second element is a loop divider.

4. A method according to claim 1 wherein the second element is a phase detector.

5. A method according to claim 1 wherein the second element is a loop filter.

6. A method according to claim 1 wherein the first response time is fixed.

7. A method according to claim 1 wherein the first response time is variable.

8. In a phase locked loop (PLL) including a plurality of elements including at least a phase detector, a loop filter, a voltage controlled oscillator, and a loop divider serially coupled to each other to form a feedback signal arrangement in the PLL, each element having a response time defined by a difference in time between a first time at which the element is enabled and a second time, occurring after the first time, at which an output signal of the element reaches a steady state condition, the PLL having a response time defined by a difference in time between a time when a disabled element of the plurality of elements is enabled and a time when an output frequency signal of the PLL reaches a steady state condition, a method for minimizing the response time of the PLL while minimizing power consumption of the PLL comprising the steps of:

enabling the voltage controlled oscillator, having a first response time responsive to a first control signal;

monitoring, directly from the first element, an indication of when an output signal of the voltage controlled oscillator has substantially reached its steady state frequency condition;

controlling a second control signal responsive to the monitored indication; and

enabling at least one of the phase detector, the loop filter, and the loop divider, each having a response time less than the first response time, responsive to the second control signal.

9. A method according to claim 8 wherein the first response time is fixed.

10. A method according to claim 8 wherein the first response time is variable.

11. In a phase locked loop (PLL) having an enabled and a disabled state responsive to a PLL state control signal, the PLL having a plurality of elements including a first element and a second element, each of the first element and the second element having an input terminal and an output terminal, the output terminal of the first element being coupled to the input terminal of the second element and the output terminal of the second element being coupled to the input terminal of the first element to form a feedback signal arrangement in the PLL, each element having a response time defined by a difference in time between a first time at which the element is enabled and a second time, occurring after the first time, at which an output signal of the element reaches a steady state condition, the PLL having a response time defined by a difference in time between a time when a disabled element of the plurality of elements is enabled and a time when an output frequency signal of the PLL reaches a steady state condition, an apparatus for minimizing the response time of the PLL while minimizing power consumption of the PLL comprising:

a controller coupled to receive the PLL state control signal and operative to produce a first control signal and a second control signal, wherein the controller enables the first element, having a first response time, responsive to the first control signal, monitors an indication, directly from the first element, of when an output signal of the first element has substantially reached its steady state frequency condition, controls a second control signal responsive to the monitored indication, and enables the second element, having a second response time less than the first response time, responsive to the second control signal.

12. An apparatus according to claim 11 wherein the first element is a voltage controlled oscillator.

13. An apparatus according to claim 11 wherein the second element is a loop divider.

14. An apparatus according to claim 11 wherein the second element is a phase detector.

15. An apparatus according to claim 11 wherein the second element is a loop filter.

16. An apparatus according to claim 11 wherein the first response time is fixed.

17. An apparatus according to claim 11 wherein the first response time is variable.

18. In a radio frequency receiver including a phase locked loop (PLL) frequency synthesizer operative to tune the radio frequency receiver to a radio frequency channel, the PLL frequency synthesizer having a plurality of elements including a first element and a second element, each of the first element and the second element having an input terminal and an output terminal, the output terminal of the first element being coupled to the input terminal of the second element and the output terminal of the second element being coupled to the input terminal of the first element to form a feedback signal arrangement in the PLL, each element having a response time defined by a difference in time between a first time at which the element is enabled and a second time, occurring after the first time, at which an output signal of the element reaches a steady state condition, the PLL having a response time defined by a difference in time between a time when a disabled element of the plurality of elements is enabled and a time when an output frequency signal of the PLL reaches a steady state condition, a method for minimizing the response time of the PLL while minimizing power consumption of the PLL comprising the steps of:

receiving a radio frequency signal to produce a received signal; and

enabling the radio frequency receiver responsive to the received signal, wherein the step of enabling the radio frequency receiver further comprises the step of;

enabling the PLL frequency synthesizer comprising the steps of;

enabling the first element, having a first response time, responsive to a first control signal;

monitoring, directly from the first element, an indication of when an output signal of the first element has substantially reached its steady state frequency condition;

controlling a second control signal responsive to the monitored indication; and

enabling the second element, having a second response time less than the first response time, responsive to the second control signal.

19. A radio frequency receiver including a phase locked loop (PLL) frequency synthesizer operative to tune the radio frequency receiver to a radio frequency channel, the PLL frequency synthesizer having a plurality of elements including a first element and a second element, each of the first element and the second element having an input terminal and an output terminal, the output terminal of the first element being coupled to the input terminal of the second element and the output terminal of the second element being coupled to the input terminal of the first element to form a feedback signal arrangement in the PLL, each element having a response time defined by a difference in time between a first time at which the element is enabled and a second time, occurring after the first time, at which an output signal of the element reaches a steady state condition, the PLL having a response time defined by a difference in time between a time when a disabled element of the plurality of elements is enabled and a time when an output frequency signal of the PLL reaches a steady state condition, the radio frequency receiver comprising:

a receiver line-up coupled to receive a radio frequency signal and operative to produce a received signal;

a processor coupled to receive the received signal and operative to produce a PLL state control signal responsive to the received signal; and

a controller coupled to receive the PLL state control signal and operative to produce a first control signal and a second control signal, wherein the controller enables the first element, having a first response time, responsive to the first control signal, monitors an indication, directly from the first element, of when an output signal of the first element has substantially reached its steady state frequency condition, controls the second control signal responsive to the monitored indication, and enables the second element, having a second response time less than the first response time, responsive to the second control signal.