Digital sliding pole fast-restore for an electrocardiograph display

• US 6,185,450 B1
• Filed: 01/26/1998
• Issued: 02/06/2001
• Est. Priority Date: 01/26/1998
• Status: Expired due to Fees

• Current Assignee: Physio-Control Incorporated (Stryker Corporation)
• Original Assignee: Physio-Control Corporation
• Inventors: Seguine, Dennis R., LaBrash, Stephen P., Stice, John R.
• Primary Examiner(s): EVANISKO, GEORGE ROBERT
• Application Number:
  US09/013,570
• Time in Patent Office: 1,107 Days
• Field of Search: 128/901, 128/902, 600/509, 600/510, 600/523, 607/4, 607/5, 607/9, 607/13
• US Class Current: 600/509
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/304 Switching circuits
• CPC Class Codes: Y10S 128/901 Suppression of noise in electric signal

Abstract

A method and apparatus for monitoring an electrocardiograph waveform, and for returning an electrocardiograph trace to the middle of a display, such as a chart recorder strip. The monitoring circuit includes an amplifier and a switch for switching the frequency response curve of the monitoring circuit. In a first position, the switch causes the monitoring circuit to have a slow frequency response curve, which allows for accurate monitoring of ECG waveforms. In a second position, the switch causes the monitoring circuit to have a fast frequency response curve, which allows the amplifier of the monitoring circuit to quickly be brought out of saturation. The amplifier of the monitoring circuit becomes saturated when a defibrillation or pace pulse has been applied to a patient who is being monitored. The switch is controlled by a pulse waveform control signal that is provided by a microprocessor. By varying the duty cycle of the control signal, the frequency response curve of the monitoring circuit can be shifted. By changing the duty cycle of the pulse waveform in incremental steps, certain problems can be avoided, such as erroneous QRS detect marks that are otherwise produced. The incremental steps in which the duty cycle of the pulse waveform is changed may be predetermined, or they may be adjusted according to feedback from the amplifier.

Claims

1. A circuit for processing ECG signals, the circuit comprising:

an amplifier for amplifying the ECG signals;

a switch coupled to the amplifier, the switch being switchable between at least two positions, the position of the switch determining the high pass frequency response of the circuit, the switch being controlled by a switch control signal;

the switch in a first position causing the circuit to have a first high pass frequency response curve with a first pole that is low enough to allow processing of ECG signals;

the switch in a second position causing the circuit to have a second high pass frequency response curve with a second pole that is high enough to cause the amplifier of the circuit to be brought out of saturation within a specified period of time;

a control program for providing the switch control signal, the switch control signal being a pulse waveform with a duty cycle, the duty cycle being adjusted in incremental steps by the control program so as to shift the high pass frequency response of the circuit in incremental steps from the second frequency response curve to the first frequency response curve; and

the control program including an adjustment routine that switches the switch to the second position and then adjusts the duty cycle of the switch control signal in incremental steps until the first frequency response curve is exhibited.

2. The circuit of claim 1, further comprising a low pass filter coupled to the amplifier, the low pass filter being added to establish a DC envelope filter with an output, and also comprising a monitoring means coupled to the low pass filter for monitoring the output of the envelope filter and providing related data.

3. The circuit of claim 2, wherein the output from the envelope filter has a baseline and the adjustment routine uses data from the monitoring means to determine if the output of the envelope filter is trending toward the baseline and, if it is, controlling the switch to change the duty cycle by fixed increments to reduce the frequency of the pole of the high pass frequency response curve so as to shift the pole in a direction going away from the second pole until either the output of the envelope filter is no longer trending toward the baseline or a predetermined limit for the duty cycle of the control signal is reached.

4. The circuit of claim 2, wherein the output from the envelope filter has a baseline and a required dynamic range and the adjustment routine uses data from the monitoring means to determine if the output of the envelope filter is trending away from the baseline and is outside of the required dynamic range and, if it is, the switch control signal controlling the switch to change the duty cycle of the control signal by fixed increments to increase the frequency of the pole of the high pass frequency response curve in a direction going toward the second pole until either the output of the envelope filter is no longer trending away from the baseline or the output of the envelope filter comes within the required dynamic range or a limit for the duty cycle of the control signal is reached.

5. The circuit of claim 1, wherein the incremental steps comprise at least three steps of progressive duty cycle percentages between unity and zero duty cycle values, comprising at least a step to a 25% duty cycle, a step to a 75% duty cycle, and a step to a 95% duty cycle.

6. The circuit of claim 1, wherein the circuit further comprises an output with DC slewing and the incremental steps comprise a sufficient number of steps of duty cycle changes so that the DC slewing of the output of the circuit that is caused by the steps does not exceed a selected level.

7. The circuit of claim 1, wherein the first pole of the first frequency response curve is at approximately 0.05 Hertz.

8. The circuit of claim 1, wherein the second pole of the second frequency response curve is at approximately 10 Hertz.

9. A circuit for processing ECG signals, the circuit comprising:

an amplifier for amplifying the ECG signals;

a switch coupled to the amplifier, the switch being switchable between at least two positions, the position of the switch determining the high pass frequency response curve of the circuit, the switch being controlled by a switch control signal;

the switch in a first position causing the circuit to have a first high pass frequency response curve with a first pole that is low enough to allow processing of ECG signals;

the switch in a second position causing the circuit to have a second high pass frequency response curve with a second pole that is high enough to cause the amplifier of the circuit to be brought out of saturation within a specified period of time;

a control program for providing the switch control signal, the switch control signal being a pulse waveform with an operating frequency and a duty cycle, the duty cycle being adjusted in incremental steps by the control program so as to shift the high pass frequency response of the circuit in incremental steps from the second frequency response curve to the first frequency response curve; and

a QRS detect mark generator coupled to the amplifier, wherein the operating frequency of the pulse waveform is above the upper frequency of a typical ECG bandwidth as a result of which adjustments to the pulse waveform duty cycle do not cause the QRS detect mark generator to produce erroneous QRS detect marks.

10. A high pass filter for processing ECG signals, the high pass filter comprising:

an output for providing the processed ECG signals;

an amplifier coupled to the output;

a control means for providing a pulse waveform with an adjustable duty cycle having at least a first level and a second level, the duty cycle of the pulse waveform determining the pole of the high pass frequency response curve of the high pass filter, the duty cycle at the first level adjusting the pole of the high pass filter to a frequency of approximately 0.05 Hertz, the duty cycle at the second level adjusting the pole of the high pass filter to a frequency that is greater than 0.05 Hertz; and

the control means including an adjustment routine that sets the duty cycle at the second level and then adjusts the duty cycle in incremental steps so as to shift the duty cycle from the second level to the first level.

11. The high pass filter of claim 10, wherein when the duty cycle is at the second level, the pole of the high pass filter is at approximately 10 Hertz.

12. The high pass filter of claim 10, further comprising a QRS detect mark generator coupled to the output, and wherein the pulse waveform comprises an operating frequency that is above the upper frequency of a typical ECG bandwidth as a result of which adjustments to the duty cycle of the pulse waveform by the control means do not cause the QRS detect mark generator to produce erroneous QRS detect marks.

13. A circuit for processing ECG signals, ECG signals having a typical bandwidth with an upper frequency, the circuit comprising:

a control circuit for providing a pulse waveform control signal with a duty cycle;

a high pass filter with an adjustable pole coupled to the control circuit;

an output coupled to the high pass filter for outputting processed ECG signals; and

a QRS detect mark generator coupled to the output, the pole of the high pass filter being adjustable by the pulse waveform control signal that is provided by the control circuit, the pulse waveform having an operating frequency that is above the upper frequency of a typical ECG bandwidth as a result of which adjustments to the duty cycle of the pulse waveform by the control circuit do not cause the QRS detect mark generator to produce erroneous QRS detect marks at the output of the circuit.

14. The circuit of claim 13, wherein the control circuit comprises a control adjustment circuit for adjusting the duty cycle and the control circuit further comprises an ECG signal processing period and a circuit recovery period, the control circuit cycling through the ECG signal processing period and the circuit recovery period and wherein during the ECG signal processing period the duty cycle of the control signal is adjusted by the control adjustment circuit to a first level so that the pole of the high pass filter is set at a frequency of approximately 0.05 Hertz so as to allow normal ECG signal processing.

15. The circuit of claim 14, wherein the high pass filter comprises an amplifier, and wherein during the circuit recovery period the duty cycle of the control signal is adjusted by the control adjustment circuit to a second level so that the pole of the high pass filter is at a frequency of approximately 10 Hertz, so as to allow the amplifier in the high pass filter to quickly be brought out of saturation.

16. A method for bringing an amplifier out of saturation in an ECG monitoring circuit, the ECG monitoring circuit having at least a first frequency response curve with a first pole for normal ECG signal processing and a second frequency response curve with a second pole for fast circuitry recovery, the circuit being controlled to move between the two frequency response curves by a pulse waveform control signal with a duty cycle that is generated by a control circuit, the circuit having the first frequency response curve when the duty cycle of the control signal is at a first level and the circuit having the second frequency response curve when the duty cycle of the control signal is at a second level, the method comprising:

(a) detecting when the amplifier has become saturated and then initially providing the pulse waveform control signal with the duty cycle of the second level; and

(b) using an adjustment routine to change the percentage of the duty cycle of the pulse waveform control signal in incremental steps from the second level to the first level, thus returning the circuit to normal ECG signal processing when the duty cycle is returned to the first level.

17. The method of claim 16, wherein the ECG monitoring circuit has DC slewing caused by the incremental steps, and wherein the number of incremental steps used by the adjustment routine is increased until the DC slewing of the ECG monitoring circuit that is caused by the steps is reduced to a selected level.

18. The method of claim 16, wherein the pulse waveform has an operating frequency that is set at a frequency that is above the upper frequency of a typical ECG bandwidth.

19. The method of claim 16, wherein the adjustment routine comprises:

(a) adding a low pass filter to establish a DC envelope filter with an output that has a baseline and a required dynamic range;

(b) monitoring the output of the envelope filter;

(c) if the output of the envelope filter is less than a threshold and trending toward the baseline, verifying whether the duty cycle of the control signal is already at a maximum and, if it is, returning to (b) and, if it is not, proceeding to (d); and

(d) increasing the duty cycle by a fixed increment and then returning to (b).

20. The method of claim 19, further comprising the steps of determining if the output of the envelope filter is trending away from the baseline and if it is outside the required dynamic range and, if it is, decreasing the duty cycle by a fixed increment and then returning to step (b) of claim 19.

21. In an ECG monitoring circuit with a high pass frequency response curve with a pole, a method for adjusting the pole of the high pass frequency response curve, the ECG monitoring circuit including an amplifier and a means for determining when the amplifier is saturated, the pole of the high pass frequency response curve being adjustable by a control circuit that produces an adjustable pulse waveform control signal with a duty cycle, the pole being at a first frequency for normal ECG monitoring when the duty cycle is at a first level and being at a second frequency for fast unsaturation of the amplifier when the duty cycle is at a second level, the method comprising:

(a) placing the duty cycle at the first level for normal ECG signal monitoring;

(b) determining when the amplifier is saturated;

(c) when the amplifier is saturated, changing the duty cycle to the second level for fast unsaturation of the amplifier; and

(d) returning the duty cycle from the second level to the first level in incremental steps.

22. The method of claim 21, wherein normal ECG signals have an upper bandwidth and wherein the pulse waveform control signal has a frequency that exceeds the frequency of the upper bandwidth of normal ECG signals.

23. The method of claim 21, wherein an adjustment routine is used to create an envelope filter with an output, and wherein the adjustment routine uses the output of the envelope filter to determine the number of incremental steps that are used to return the duty cycle from the second level to the first level.