Single chip protocol engine and data formatter apparatus for off chip host memory to local memory transfer and conversion

• US 6,185,620 B1
• Filed: 04/03/1998
• Issued: 02/06/2001
• Est. Priority Date: 04/03/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Johnson, Stephen M., Adams, John M., Hoglund, Timothy E., Weber, David M., Reber, Mark A.
• Primary Examiner(s): Matar, Ahmad F.
• Assistant Examiner(s): THOMSON, WILLIAM D
• Application Number:
  US09/054,849
• Time in Patent Office: 1,040 Days
• Field of Search: 709/232, 709/231, 709/230, 709/250, 709/251, 710/105, 710/11, 710/106, 714/4, 714/49, 370/222, 370/216
• US Class Current: 709/230
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9031 Wraparound memory, e.g. overrun or underrun detection
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A method and apparatus for transferring data from a host to a node through a fabric connecting the host to the node. A chip architecture is provided in which a protocol engine provides for on ship processing in transferring data such that frequent interrupts from various components within the chip may be processed without intervention from the host processor. Additionally, context managers are provided to transmit and receive data. The protocol engine creates a list of transmit activities, which is traversed by the context managers, which in turn execute the listed activity in a fashion independent from the protocol engine. In receiving data, the context managers provide a mechanism to process frames of data originating from various sources without requiring intervention from the protocol engine. When receiving data, the context managers are able to process frames from different sources, which arrive out of order. Additionally, the context managers also determine when all frames within a sequence have been received. A link control unit is provided in which loop management is provided when the host is connected to a loop. Management of the loop includes implementing mechanisms to initiate acquisition of the loop and initiate a release of the loop in response to conditions in which data is received and transmitted by the host and by other nodes on the loop.

Claims

1. A chip comprising:

an input port;

an output port;

a first processing unit, wherein the first processing unit includes;

first reception means for receiving request from a host located off the chip to transmit data to a destination;

storage means for storing the destination and the data in a memory connected to the chip prior to transmission to the destination;

generation means for generating a list of data transfers for data stored in the memory, wherein the list includes and identification of the data and a destination for the data; and

a second processing unit, wherein the second processing unit includes;

detection means for detecting a presence of data for transmission to a destination using the list o data transfers generated by the generation means to detect a presence of data for transmission; and

formatting means for formatting the data into a format for transport to the destination using the data and the destination.

2. The chip of claim 1, wherein a list of expected data is generated by the first processing unit and wherein the second processing unit includes:

reception means for receiving data from a remote source;

identification means for storing the data; and

indication means for indicating to the first processing unit when all data has been received from the remote source.

3. The chip architecture of claim 1, wherein the second processing unit is an embedded processor.

4. The chip architecture of claim 1, wherein the second processing unit is a state machine.

5. The chip of claim 1, wherein the second reception means comprises:

transfer means for transferring data from a host memory to a memory coupled to the chip.

6. The chip of claim 1, wherein the input port is configured for communication with a bus on a host system, while the output port is configure for communication with the destination.

7. A chip comprising:

a bus interface unit, wherein the bus interface unit sends and receives data from a bus on the host;

a protocol engine connected to the bus interface unit, wherein the protocol engine manages transfer of information from a host memory coupled to the bus to a local memory coupled to the chip and generates a list of transmit activities used to transmit data to a device;

a link controller, wherein the link controller provides an interface for a communications link to the device;

a transmitter connected to the link controller, wherein the transmitter manages formatting data in to a format for transfer to the device by the link controller;

a receiver connected to the link controller, wherein the receiver managers data received by the link controller; and

a context manager coupled to the protocol engine, wherein the context manager traverses the list of transmit activities and executes a transfer of data based on the list using the transmitter and wherein the context manager processes data received by the receiver.

8. The chip of claim 7, wherein the protocol engine is an embedded processor.

9. The chip of claim 8, wherein the context manager is an embedded processor.

10. The chip of claim 8, wherein the context manager is a state machine.

11. The chip of claim 7, wherein the data is a form of frames and wherein the context manager processes frames received from different sources arriving out of order.

12. The chip of claim 7, wherein the context manager traverses the list of transmit activities and executes a transfer of data by reading a first item from the list of transmit activities, determines whether the data for the item is local data, writes the data from the local memory to the transmitter in response to a determination that the data is local.

13. The chip of claim 12, wherein the context manager loads data, across the bus, from the host memory into the transmitter in response to a determination that the data for the item is system data.

14. The chip of claim 13, wherein the transmitter includes storage for storing data and context information and a framer connected to the storage.

15. The chip of claim 12, wherein the list of transmit activities is a plurality of transmit control blocks.

16. A chip comprising:

a bus interface unit, wherein the bus interface unit provides an interface to send and receive data from a first bus on the host;

a protocol engine connected to the bus interface unit, wherein the protocol engine manages transfer of information from a host memory to a memory coupled to the chip and responsive to a request to transfer data, wherein the protocol engine has a plurality of modes of operation comprising;

a first mode of operation in which the protocol engine detects a request to transfer block of data located in a host memory; and

a second mode of operation, responsive to detecting the request, in which the protocol engine moves the block of data from the host memory into a local memory and creates a transmit block, wherein the transmit block includes the block of data and information used to transmit the block of data;

a transfer engine, wherein the transfer engine detects the transmit block and sends the transmit block to a transmitter;

the transmitter receives the transmit block and places block of data into a format for transmission, wherein the format is identified from the information; and

a link controller connected to the transmitter, wherein the link controller provides an interface for a communications link to the device.

17. The chip of claim 16, wherein the context information includes an identification of a path to a destination.

18. The chip of claim 16, wherein the link controller is configured for communication with a Fibre channel arbitrated loop.