Data transfer controller employing differing memory interface protocols dependent upon external input at predetermined time

• US 6,185,629 B1
• Filed: 03/08/1994
• Issued: 02/06/2001
• Est. Priority Date: 03/08/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Robertson, Iain, Simpson, Richard, Balmer, Keith
• Primary Examiner(s): VU, VIET DUY
• Application Number:
  US08/208,517
• Time in Patent Office: 2,527 Days
• Field of Search: 710/10, 710/13, 710/52, 710/127, 710/8, 710/25, 710/126, 711/1, 711/5, 711/170, 711/201, 395/527
• US Class Current: 710/10
• CPC Class Codes: G06F 12/0215 with look ahead addressing means

Abstract

This invention is a data processing apparatus which may interface with plural types of memories. A static decoder coupled to an external port decodes signals which from an external source that indicate the type of memory. Interface circuitry receives coded information from the static decoder and selects a protocol for information transfer. In the preferred embodiment, the protocol includes addressing information having multiplexed row/column addresses for accessing dynamic memories or un-multiplexed addresses for accessing static memories. The interface circuitry further includes a column address shifter. The column address shifter shifts address bits to vary the number of bits available for column addressing. The data processing apparatus attempts to use page mode addressing whenever possible. A lastpage register coupled to the address generator for stores previous address information. A comparator compares the previous address information stored in the lastpage register to the current address. If no page change is detected, the data processor supplies only the column address to the memory in a page mode cycle, or else the data processor supplies a full new address including both the row address and the column address. The data processing apparatus may also control the number of bits transferred. An external port supplies a bus size signal to a static decoder. The interface circuitry selects a a bus size protocol based upon the received bus size signal.

Claims

1. A image processor comprising:

a data processor having a plurality of first address lines and a plurality of first data lines, said data processor supplying an address on said plurality of first address lines and transferring data via said plurality of data lines;

an external port having a plurality of second address lines, a plurality of second data lines, a plurality of memory control output lines and a plurality of bus size input lines; and

a data buffer connected to said first data lines of said data processor; and

memory interface circuitry coupled to said data processor, to said external port and to said data buffer operative to transfer information between said data processor and said external port, said memory interface circuitry including;

an addressing means receiving a data processor address on said plurality of first address lines of said data processor and supplying said data processor address to said plurality of second address lines of said external port for output;

a decoding circuit connected to said bus size input lines for sampling input on said bus size input lines at a predetermined time in a memory cycle following supply of said data processor address for decoding said sampled inputs from said bus size input lines of said external port to indicate a bus size protocol for transfers of information;

a data circuit supplying data from said data buffer to a predetermined set of said second address lines of said external port corresponding to said bus size indicated by said bus size input lines in a quantity of bits corresponding to said bus size indicated by said bus size input lines and supplying no data on other of said second address lines of said external port.

2. The image processor of claim 1 wherein said decoding circuit further establishes the size in bits of the transfers to accommodate the bus size thus determined.

3. A data processing system comprising:

a data processor having a plurality of first address lines and a plurality of first data lines, said data processor supplying an address on said plurality of first address lines and transferring data via said plurality of data lines;

an external port having a plurality of second address lines, a plurality of second data lines, a plurality of memory control output lines and a plurality of memory protocol input lines; and

a memory interface controller coupled to said data processor and said external port operative to transfer information between said data processor and said external port, said memory interface circuitry

supplying signals on said plurality of first address lines of said data processor specifying a data processor address to said plurality of second address lines of said external port,

sampling inputs on said memory protocol input lines at a predetermined time in a memory cycle following supply of said data processor address, and

supplying address signals to said plurality of second address lines of said external port and supplying memory control signals to said plurality of memory control output lines of said external port for control of information transfer between said data processor and said external port for a next memory cycle corresponding to said sampled inputs.

4. The data processing system of claim 3 wherein

said predetermined time in a memory cycle at which said memory interface controller samples said memory protocol input lines is a row address time during which said memory interface controller supplies a row address on said second address lines of said external port.

5. The data processing system of claim 3 wherein:

said plurality of memory protocol input lines of said external port includes a plurality of address shift selection input lines indicating no address shift or a predetermined address shift;

said memory interface controller

supplying said address received on said first address lines from said data processor to said second address lines of said external port during a row address time,

again supplying said address received on said first address lines from said data processor to said second address lines of said external port during a column address time if said sampled inputs of said plurality of address shift selection input lines indicate no address shift, and

supplying said address received on said first address lines from said data processor shifted a predetermined shift amount to said second address lines of said external port during a column address time if said sampled inputs of said plurality of address shift selection input lines indicate a predetermined address shift.

6. The data processing system of claim 3 wherein:

said plurality of memory protocol input lines of said external port includes a plurality of page size input lines indicating a page size;

said data processing system further comprises

a lastpage register coupled to said plurality of first address lines of said data processor for storing previous address information; and

a comparator connected to said plurality of first address lines of said data processors and said lastpage register, having a number of bits to compare input, said comparator comparing a number of lines of said plurality of first address lines of said data processors to corresponding bits of said lastpage register and generating a new page signal upon a failure to match; and

said memory interface controller is connected to said comparator, said memory interface controller

supplying said number of bits to compare input of said comparator corresponding to a page size indicated by said plurality of page size input lines;

supplying memory control signals to said plurality of memory control output lines of said external port for a memory page mode access if said comparator does not generate said new page signal, and

supplying memory control signals to said plurality of memory control output lines of said external port for a normal row/column access if said comparator generates said new page signal.

7. The data processing system of claim 6 wherein:

said page size indicated by said plurality of page size input lines includes a no page indication;

said memory interface controller

supplying memory control signals to said plurality of memory control output lines of said external port for a normal row/column access if said plurality of page size input lines indicates no page.

8. The data processing system of claim 3 wherein:

said plurality of memory protocol input lines of said external port includes a plurality of column timing input lines indicating a number of cycles for a column address time; and

said memory interface controller

supplying a column address for a number of cycles corresponding to said number of cycles for a column address time indicated by said column timing input lines.

9. The data processing system of claim 3 wherein:

said plurality of memory protocol input lines of said external port includes a plurality of bus size input lines indicating a bus size;

said data processing system further comprises

a data buffer connected to said first data lines of said data processor; and

said memory interface controller is connected to said data buffer, said memory interface controller

supplying data from said data buffer to a predetermined set of said second address lines of said external port corresponding to said bus size indicated by said bus size input lines in a quantity of bits corresponding to said bus size indicated by said bus size input lines and supplying no data on other of said second address lines of said external port.

10. The data processing system of claim 9 further comprising:

an endian mode memory storing an indication of either a little endian mode or a big endian mode;

said memory interface controller is connected to said endian mode memory, said memory interface controller

supplying data from said data buffer to a predetermined number of least significant bits of said second address lines of said external port corresponding to said bus size indicated by said bus size input lines and supplying no data on other of said second address lines of said external port when said endian mode memory indicates little endian mode, and

supplying data from said data buffer to a predetermined number of most significant bits of said second address lines of said external port corresponding to said bus size indicated by said bus size input lines and supplying no data on other of said second address lines of said external port when said endian mode memory indicates big endian mode.

11. The data processing system of claim 3 wherein

said data processor, said external port and said memory interface controller are disposed on a single integrated circuit.

12. A data processing system comprising:

a data processor having a plurality of first address lines and a plurality of first data lines, said data processor supplying an address on said plurality of first address lines and transferring data via said plurality of data lines;

an external memory storing data at a plurality of addressable memory locations having a plurality of second address lines, a plurality of second data lines, a plurality of memory control lines and a plurality of memory protocol lines; and

a memory interface controller coupled to said data processor and said external memory operative to transfer information between said data processor and said external memory, said memory interface circuitry

supplying signals on said plurality of first address lines of said data processor specifying a data processor address to said plurality of second address lines of said external memory,

sampling inputs on said memory protocol input lines at a predetermined time in a memory cycle following supply of said data processor address, and

supplying address signals to said plurality of second address lines of said external memory and supplying memory control signals to said plurality of memory control lines of said external memory for control of information transfer between said data processor and said external memory for a next memory cycle corresponding to said sampled inputs.

13. The data processing system of claim 12 wherein

said predetermined time in a memory cycle at which said memory interface controller samples said memory protocol lines is a row address time during which said memory interface controller supplies a row address on said second address lines of said external memory.

14. The data processing system of claim 12 wherein:

said plurality of memory protocol lines of said external memory includes a plurality of address shift selection lines indicating no address shift or a predetermined address shift;

said memory interface controller

supplying said address received on said first address lines from said data processor to said second address lines of said external memory during a row address time,

again supplying said address received on said first address lines from said data processor to said second address lines of said external memory during a column address time if said sampled inputs of said plurality of address shift selection lines indicate no address shift, and

supplying said address received on said first address lines from said data processor shifted a predetermined shift amount to said second address lines of said external memory during a column address time if said sampled inputs of said plurality of address shift selection lines indicate a predetermined address shift.

15. The data processing system of claim 12 wherein:

said plurality of memory protocol lines of said external memory includes a plurality of page size lines indicating a page size;

said data processing system further comprises

a lastpage register coupled to said plurality of first address lines of said data processor for storing previous address information; and

a comparator connected to said plurality of first address lines of said data processors and said lastpage register, having a number of bits to compare input, said comparator comparing a number of lines of said plurality of first address lines of said data processors to corresponding bits of said lastpage register and generating a new page signal upon a failure to match; and

said memory interface controller is connected to said comparator, said memory interface controller

supplying said number of bits to compare input of said comparator corresponding to a page size indicated by said plurality of page size lines;

supplying signals to said memory control lines of said external memory for a memory page mode access if said comparator does not generate said new page signal, and

supplying signals to said memory control lines of said external memory for a normal row/column access if said comparator generates said new page signal.

16. The data processing system of claim 15 wherein:

said page size indicated by said plurality of page size input lines includes a no page indication;

said memory interface controller

supplying signals to said memory control lines of said external memory for a normal row/column access if said plurality of page size lines indicates no page.

17. The data processing system of claim 12 wherein:

said plurality of memory protocol lines of said external memory includes a plurality of column timing lines indicating a number of cycles for a column address time; and

said memory interface controller

supplying a column address for a number of cycles corresponding to said number of cycles for a column address time indicated by said column timing lines.

18. The data processing system of claim 12 wherein:

said plurality of memory protocol lines of said external memory includes a plurality of bus size lines indicating a bus size;

said data processing system further comprises

a data buffer connected to said first data lines of said data processor; and

said memory interface controller is connected to said data buffer, said memory interface controller

supplying data from said data buffer to a predetermined set of said second address lines of said external memory corresponding to said bus size indicated by said bus size lines in a quantity of bits corresponding to said bus size indicated by said bus size lines and supplying no data on other of said second address lines of said external memory.

19. The data processing system of claim 18 further comprising:

an endian mode memory storing an indication of either a little endian mode or a big endian mode;

said memory interface controller is connected to said endian mode memory, said memory interface controller

supplying data from said data buffer to a predetermined number of least significant bits of said second address lines of said external memory corresponding to said bus size indicated by said bus size lines and supplying no data on other of said second address lines of said external memory when said endian mode memory indicates little endian mode, and

supplying data from said data buffer to a predetermined number of most significant bits of said second address lines of said external memory corresponding to said bus size indicated by said bus size lines and supplying no data on other of said second address lines of said external memory when said endian mode memory indicates big endian mode.

20. The data processing system of claim 12 wherein

said data processor and said memory interface controller are disposed on a single integrated circuit.