Bus for high frequency operation with backward compatibility and hot-plug ability

• US 6,185,642 B1
• Filed: 07/15/1998
• Issued: 02/06/2001
• Est. Priority Date: 07/15/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Thurber, Steven Mark, Fuhs, Ronald Edward, Beukema, Bruce Leroy, Neal, Danny Marvin, Kelley, Richard Allen
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Cao, Chun
• Application Number:
  US09/116,058
• Time in Patent Office: 937 Days
• Field of Search: 710/33, 710/60, 710/62, 710/100, 710/103, 713/400, 713/500, 713/501, 713/600, 709/233
• US Class Current: 710/60
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004

Abstract

A peripheral interconnect for a computer system comprising a bridge, a peripheral bus, and a peripheral device, wherein at least one of these components is adapted to selectively operate in either a high performance mode or a low performance mode, the high performance mode using a first operating speed and a first protocol, and the low performance mode using a second operating speed which is lower than said first operating speed, and a second protocol which is different from the first protocol. The disclosed embodiment provides a high performance mode with a 100 MHz speed and a protocol that disallows pacing, and a low performance mode that uses a 66 MHz or 33 MHz speed and a standard PCI protocol that allows pacing. The high performance operating speed can be twice the low performance operating speed, by doubling the clock frequency and clocking data on only one clock edge, or by clocking data on both a rising edge and a falling edge of a clock signal while operating at the lower clock frequency. High performance adapters can provide split transaction capability, with a high performance bridge having the ability to support split transactions or alias split transactions to delayed transactions. Backward compatibility may also be provided for optional features such as hot-pluggability.

Claims

1. A method of providing selectable data transmission speeds between a peripheral device and a system bus of a computer system, said method comprising the steps of:

connecting a bridge to the system bus, said bridge being capable of transmitting data at a plurality of transmission speeds;

coupling said peripheral device to said bridge trough a peripheral bus, said peripheral device and said peripheral bus being capable of transmitting data at a plurality of transmission speeds;

determining a transmission speed common to all of said peripheral device, said peripheral bus, and said bridge to transmit data, said transmission speed having an associated performance mode with a transmission control protocol; and

setting an effective transmission speed of said bridge, said peripheral bus and said peripheral device by clocking data on both a rising edge and a falling edge of a clock signal.

2. The method of claim 1, wherein when said common transmission speed is a first transmission speed, which has a low performance mode and a first transmission protocol, and wherein said determining step determines that at least one of said peripheral device, said peripheral bus, and said bridge is limited to operate in said low performance mode said method includes the steps of:

selecting said low performance mode to transmit said data; and

operating said bridge, said peripheral bus and said peripheral device in said low performance mode.

3. The method of claim 1, wherein when said common transmission speed is a second transmission speed, which has a high performance mode and a second transmission protocol, said method includes the steps of:

selecting said high performance mode to transmit said data; and

operating said bridge, said peripheral bus and said peripheral device in said high performance mode.

4. The method of claim 1, wherein said step of connecting said peripheral device to said peripheral bus includes the steps of:

connecting a slot to said peripheral bus; and

inserting said peripheral device into said slot.

5. The method of claim 4, wherein said step of connecting said peripheral device to said peripheral bus includes the further steps of:

isolating said slot from said peripheral bus before said inserting step;

applying a reset signal to said slot, after said inserting step; and

initializing said peripheral device in response to said applying step.

6. The method of claim 1, wherein said bridge is adapted to selectively operate in either a high performance mode or a low performance mode, said method further comprising the steps of:

determining that at least one of said peripheral bus and said peripheral device is limited to operation in said low performance mode; and

in response to said determining step, selecting said low performance mode for operating said bridge, and operating said peripheral bus and said peripheral device in said low performance mode.

7. The method of claim 6, further comprising the steps of:

determining that said peripheral bus and said peripheral device operate in said high performance mode; and

in response to said determining step, selecting said high performance mode for operating said bridge, and operating said peripheral bus and said peripheral device in said high performance mode.

8. The method of claim 7, wherein said operating step operates said bridge, said peripheral bus and said peripheral device in said high performance mode at said first operating speed which is approximately twice said second operating speed, by clocking data on only one clock edge of a clock signal.

9. The method of claim 7, wherein said operating step operates said bridge, said peripheral bus, and said peripheral device in said high performance mode at said first operating speed which is approximately twice said second operating speed, by clocking data on both a rising edge and a falling edge of a clock signal which is also used for said second operating speed.

10. The method of claim 1, wherein said peripheral device is adapted to selectively operate in either a high performance mode or a low performance mode, said method further comprising the step of in response to determining that at least one of said peripheral bus and said bridge is limited to operation in said low performance mode, selecting said low performance mode for operating said bridge, and operating said peripheral bus and said peripheral device in said low performance mode.

11. The method of claim 1, wherein said peripheral bus is adapted to selectively operate in either a high performance mode or a low performance mode, said method further comprising the step of in response to determining that at least one of said peripheral device and said bridge is limited to operation in said low performance mode, selecting said low performance mode for operating said bridge, and operating said peripheral bus and said peripheral device in said low performance mode.

12. A computer system comprising:

a system bus;

a memory device connected to said system bus;

processor means, connected to said system bus, for carrying out program instructions stored in said memory device;

a bridge connected to said system bus, wherein said bridge is adapted to selectively operate in either a high performance mode or a low performance mode and includes a pin to receive an indication of whether said peripheral bus and said peripheral device may operate at a first operating speed and a second operating speed that is less than the first operating speed;

a peripheral bus connected to said bridge, said peripheral bus operating at a particular data transmission rate;

a peripheral device connected to said peripheral bus;

means for determining when all of said peripheral device, said peripheral bus, and said bridge are adapted to operate at the first operating speed; and

means for operating at said first operating speed by clocking data on both a rising edge and a falling edge of a clock signal.

13. The computer system of claim 12, wherein:

said peripheral device is adapted to selectively operate in either said high performance mode or said low performance mode; and

said peripheral device includes a pin to indicate whether said peripheral device may be operated in said high performance mode.

14. The computer system of claim 12, wherein when said determining means determines that each of said bridge, said peripheral bus, and said peripheral device operate in a high performance mode, which has a transmission control protocol corresponding to a faster data transmission speed than said low performance mode, wherein further said particular data transmission rate is at least equal to a rate associated with said high performance mode.

15. The computer system of claim 14, further comprising means for generating said first operating speed at approximately twice said second operating speed, by clocking data on only one clock edge of a clock signal.

16. The computer system of claim 12, wherein said peripheral device is connected to said peripheral bus using a slot and further comprising means for isolating said slot from said peripheral bus before said peripheral device is inserted in said slot.

17. The computer system of claim 12 wherein:

said peripheral device provides split transaction capability; and

said bridge includes means for supporting split transactions and aliasing split transactions to delayed transactions.

22. The computer system of claim 12, wherein when said determining means determines that at least one of said bridge, said peripheral bus, and said peripheral device is adapted to operate in a low performance mode, said computer system has means for selecting said low performance mode for transmission of data to and from said peripheral device.

23. The computer system of claim 12, wherein said peripheral bus is a high performance bus and said bridge and peripheral device are low performance devices, wherein said means for selecting selects a low performance operating mode for data transmission.

24. The computer system of claim 12, wherein said peripheral bus is a low performance bus and said bridge and peripheral device are high performance devices, wherein said means for selecting selects a low performance operating mode for data transmission.

18. A system for providing selectable operation protocols and associated data transmission speeds between a peripheral device and system bus of a computer system, said system comprising:

a peripheral bus designed for transmitting data with at least one of multiple transmission speeds including a first transmission speed associated with a first protocol and a second transmission speed associated with a second protocol, wherein said second transmission speed is faster than said first transmission speed;

a peripheral device connected to said peripheral bus, said peripheral device operating at one of said first transmission speed and said second transmission speed;

a hot plug controller coupled to a plurality of slots utilized to connect said peripheral device to said peripheral bus and which monitors said device for operation characteristics including transmission speed;

a bridge, coupled to said system bus and to said hot plug controller, said bridge including a control mechanism by which a transmission speed on said peripheral bus is selected for data transmission to and from said peripheral device based on operational limitations imposed by one or more of said peripheral device, peripheral bus, or bridge.

19. The system of claim 18 further including a hot plug switch, wherein said hot plug controller is first coupled to said hot plug switch, and said hot plug switch is further coupled to said slot and said peripheral bus, wherein said hot plug controller selects said peripheral device from among multiple devices by powering up and down said slot associated with said peripheral device utilizing said hot plug switch.

20. The system of claim 18 further including a reset signal bus coupled to said bridge and said hot plug switch and which provides a reset signal input to reset a transmission rate of said peripheral bus, said bridge and said device to a transmission rate of said peripheral bus.

21. The system of claim 18, wherein said control mechanism of said bridge includes a clock logic with high pin and low pin inputs, wherein said high pin input and low pin input are utilized to select a protocol type and operating speed for said peripheral bus, said driver, and said peripheral device.

25. A method of providing backward compatibility for a high performance Peripheral Component Interconnect (PCI) bus within a data processing system, said method comprising the steps of:

connecting a bridge to a system bus of said data processing system;

connecting a PCI bus to said bridge;

connecting a peripheral device to said peripheral bus;

determining a performance mode common to all of said peripheral device, said PCI bus, and said bridge, wherein said performance mode transmits data at a particular speed utilizing an associated transmission protocol; and

transmitting data between said bridge and said peripheral device utilizing said common performance mode, wherein when said performances mode is a low performance mode, said data is transmitted at a first speed with a standard transmission protocol and when said performance mode is a high performance mode, said data is transmitted at a second speed, which is faster than said first speed and with a second transmission protocol that operates the PCI bus at higher clock rates by prohibiting pacing between data cycles.

26. The method of claim 25, wherein said transmitting step further comprises the step of inserting a cycle in both the address/command phase and a termination phase of a transfer of data via said PCI bus to enable backward compatibility.

27. The method of claim 25, further comprising the step of enabling said second transfer protocol to change from said low performance mode to said high performance mode.

28. The method of claim 27, wherein said bridge includes a plurality of pins utilized to select the transmission protocol, wherein said enabling step includes the step of automatically setting a pin of said bridge to a selected value when said second transmission protocol is desired.

29. The method of claim 25, wherein response to determining that at least one of said peripheral device, said PCI bus, and said bridge is limited to operate in said low performance mode, said method includes the steps of:

selecting said low performance mode to transmit said data; and

operating said bridge, said peripheral bus and said peripheral device in said low performance mode.

30. The method of claim 25, wherein in response to determining that all of said peripheral device, said PCI bus, and said bridge can operate in said high performance mode, said method includes the steps of:

selecting said high performance mode to transmit said data; and

operating said bridge, said peripheral bus and said peripheral device in said high performance mode.