Memory system including a plurality of memory devices and a transceiver device

• US 6,185,644 B1
• Filed: 01/19/2000
• Issued: 02/06/2001
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/487,524
• Time in Patent Office: 384 Days
• Field of Search: 710/101, 710/104, 710/102, 365/189.01, 365/189.05, 365/230.03, 365/230.04, 365/230.08
• US Class Current: 710/301
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A memory system having a master device and a plurality of memory subsystems, including first and second memory subsystems coupled to a first bus. Each memory subsystem includes a plurality of memory devices. The master device transmits a request for a read operation onto the first bus to access data from at least one memory device included in at least one memory subsystem. The first and second memory subsystems each include a transceiver device, a bus, and first and second memory devices. Each transceiver device connects to the first bus. The bus of each memory subsystem connects to each respective transceiver device, wherein each transceiver device is coupled between the first bus and each respective memory subsystem bus. The first and second memory devices in each memory subsystem are coupled respective transceiver devices via respective buses.

Claims

1. A memory system having a master device and a plurality of memory subsystems coupled to a first bus, each memory subsystem having a plurality of memory devices, wherein the master device transmits a request for a read operation onto the first bus to access data from at least one memory device included in at least one memory subsystem, the memory system comprising:

a first memory subsystem including;

a transceiver device connected to the first bus;

a subsystem bus connected to the transceiver device, wherein the transceiver device is coupled between the first bus and the subsystem bus;

a plurality of termination elements connected to the subsystem bus; and

a first and second memory device coupled to the first transceiver device via the subsystem bus.

2. The memory system of claim 1 further including a first and second circuit board, wherein the first memory subsystem is disposed on the first circuit board.

3. The memory system of claim 1 wherein the subsystem bus of the first memory subsystem further includes a first clock line, and the first and second memory devices each include clock receiver circuitry coupled to the first clock line to receive a first external clock signal.

4. The memory system of claim 3 wherein the first and second memory devices each further include a plurality of output drivers connected to the subsystem bus, wherein the plurality of output drivers of one of the first and second memory devices outputs data synchronously with respect to the first external clock signal.

5. The memory system of claim 3 wherein the subsystem bus includes a second clock line and the first clock receiver circuitry further receives a second external clock signal from the second clock line, and wherein the first and second memory devices each further include an output driver connected to the subsystem bus, wherein the output driver of one of the first and second memory devices outputs first data synchronously with respect to the first external clock signal and second data synchronously with respect to the second external clock signal.

6. The memory system of claim 5, wherein the first and second memory devices each further include delay lock loop circuitry coupled to the clock receiver circuitry and the output driver.

7. The memory system of claim 3 wherein the first and second memory devices each further include:

a plurality of output drivers connected to the subsystem bus, wherein the plurality of output drivers of the first and second memory devices output data synchronously with respect to the first external clock signal; and

delay lock loop circuitry coupled to the clock receiver circuitry and the output drivers.

8. A memory system having a controller device coupled to a first bus, and a plurality of synchronous memory devices, the memory system comprising:

a transceiver device connected to the first bus;

a second bus connected to the first transceiver device, the second bus including a first clock line, and wherein the transceiver device is coupled between the second bus and the first bus;

a first memory device having clock receiver circuitry and at least one memory section, wherein the clock receiver circuitry is connected to the first clock line; and

a second memory device having clock receiver circuitry and at least one memory section, wherein the clock receiver circuitry is connected to the first clock line.

9. The memory system of claim 8, wherein the first and second memory devices both further include output driver circuitry to output data synchronously with respect to a first clock signal.

10. The memory system of claim 9, wherein the second bus includes a second clock line wherein both the clock receiver circuitry of the first memory device and the clock receiver of the second memory device are each connected to the second clock line to receive a second external clock signal, and wherein the output driver circuitry outputs first data synchronously with respect to the first clock signal and second data synchronously with respect to the second clock signal.

11. The memory system of claim 10, wherein the first and second memory device each further include delay lock loop circuitry coupled between the clock receiver circuitry and the output driver circuitry.

12. The memory system of claim 8, wherein the clock receiver circuitry of the first and second memory devices receives a first clock signal from the first clock line, and wherein the first and second memory device each output data onto the second bus after a number of clock cycles of the first clock signal transpires.

13. The memory system of claim 8 wherein the first and second memory devices each further include a register to store a value representative of a number of clock cycles of the first clock signal to transpire before data is output during a read operation.

14. The memory system of claim 8 further including a first circuit board and a second circuit board, wherein the controller device is disposed on the first circuit board, and the plurality of memory devices are disposed on the second circuit board.

15. A memory module having a plurality of synchronous memory devices, each memory device having an array of memory cells, the memory module comprising:

a bus having a plurality of signal lines, including a first clock line;

a transceiver device coupled to the bus;

a first synchronous memory device including;

clock receiver circuitry, coupled to the first clock line, to receive a first clock signal;

output driver circuitry coupled to the bus, to output data onto the bus synchronously with respect to the first clock signal; and

a second synchronous memory device including;

clock receiver circuitry, coupled to the first clock line, to receive a first clock signal; and

output driver circuitry coupled to the bus, to output data onto the bus synchronously with respect to the first clock signal.

16. The memory module of claim 15 wherein the first and second memory devices each further include a register to store a value representative of a number of clock cycles of the first clock signal to transpire before the data is output.

17. The memory module of claim 15 wherein the bus further includes a second clock line, and wherein the clock receiver circuitry of the first and second memory device receives a second clock signal from the second clock line, wherein first data is output synchronously with respect to the first clock signal and second data is output synchronously with respect to the second clock signal.

18. The memory module of claim 17 wherein the first and second memory devices each further include delay lock loop circuitry coupled to the clock receiver circuitry and the output driver circuitry.

19. The memory module of claim 17 further including a clock generator coupled to the first and second clock line, the clock generator generating the first and second clock signals.

20. The memory module of claim 15 further including a clock generator coupled to the first clock line, the clock generator generating the first clock signal.

21. The memory module of claim 15 further including a plurality of termination elements coupled to the bus, wherein each termination element terminates a respective signal line of the plurality of signal lines.

22. The memory module of claim 15 wherein the clock receiver circuitry of the first and second memory devices include an amplifier to receive small voltage swing signals from the first clock line.