Method and apparatus for direct access test of embedded memory

• US 6,185,703 B1
• Filed: 10/10/1997
• Issued: 02/06/2001
• Est. Priority Date: 10/10/1997
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cleary, James M., Israeli, Tsafrir, Guddat, Douglas A.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): Verbrugge, Kevin
• Application Number:
  US08/948,716
• Time in Patent Office: 1,215 Days
• Field of Search: 711/3, 711/118, 395/183.01, 395/183.18, 714/25, 714/42, 714/718
• US Class Current: 714/718
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

An apparatus includes an embedded memory, a plurality of input connectors to receive input signals from an external source, a plurality of output connectors to provide output signals to the external source, and a plurality of reconfigurable input and output signal paths coupled to the embedded memory and the plurality of input and output connectors. When the apparatus is operating in a first operating mode, the plurality of reconfigurable input and output signal paths provide the input signals directly to and the output signals directly from the embedded memory.

Claims

1. A microprocessor comprising:

an embedded memory, the embedded memory including a tag memory;

a plurality of input connectors to receive input signals from an external bus;

a plurality of output connectors to provide output signals to the external bus;

a plurality of reconfigurable input and output signal paths, coupled to the embedded memory and the plurality of input and output connectors, which, when the microprocessor is operating in a direct access test mode, provide the input signals from an external bus directly to the embedded memory and the output signals directly from the embedded memory to the external bus and disable normal operation of the microprocessor;

a dedicated memory test queue, coupled to the plurality of reconfigurable input and output signal paths, configured to receive and store a plurality of memory testing commands when coupled to the external bus in a single external bus clock cycle; and

dedicated direct access test mode control logic, coupled to the dedicated memory test queue, configured to provide the plurality of memory testing commands to the embedded memory serially over a plurality of consecutive microprocessor clock cycles, the plurality of microprocessor clock cycles being equal in duration to the single external bus clock cycle.

2. The microprocessor of claim 1, wherein the plurality of reconfigurable input and output signal paths are configured to prevent the input signals from being directly input to the embedded memory when in a second operating mode.

3. The microprocessor of claim 1, wherein the embedded memory includes a plurality of cache memory arrays.

4. The microprocessor of claim 1, wherein the dedicated memory test queue is further operative to receive and store array, set, and way information corresponding to each of the plurality of commands.

5. A system comprising:

a bus configured to generate a bus clock cycle of a first duration; and

an apparatus configured to generate an apparatus clock cycle of a second duration and coupled to the bus, the apparatus including,

an embedded memory,

a plurality of input connectors to receive input signals from the bus;

a plurality of output connectors to provide output signals to the bus; and

a plurality of reconfigurable input and output signal paths, coupled to the embedded memory and the plurality of input and output connectors configured to provide the input signals directly to and the output signals directly from the embedded memory when the apparatus is operating in a direct access test mode,

a plurality of latches, coupled to the plurality of reconfigurable input and output signal paths, to receive and store a plurality of memory testing commands from the bus in a single bus clock cycle, and

test mode control logic, coupled to the plurality of latches, to provide the plurality of memory testing commands to the embedded memory serially over a plurality of apparatus clock cycles, wherein the first duration is a multiple of the second duration.

6. The system of claim 5, wherein the plurality of reconfigurable input and output signal paths are configured to prevent the input signals from being directly input to the embedded memory when the apparatus is operating in a second operating mode.

7. The system of claim 5, wherein the plurality of latches are further configured to receive and store array, set, and way information corresponding to each of the plurality of commands.

8. A method of operating a microprocessor comprising:

checking whether a direct access test mode is selected;

receiving input signals from an external source;

providing the input signals directly to an embedded memory if the direct access test mode is selected;

receiving a plurality of memory testing commands in a single bus clock cycle, the bus clock cycle having a first duration;

storing the plurality of memory testing commands in a memory test queue; and

providing the plurality of memory testing commands to the embedded memory serially over a plurality of microprocessor clock cycles, a microprocessor clock cycle of the plurality of microprocessor clock cycles having a second duration, wherein the second duration is a fraction of the first duration.

9. The method of claim 8, further comprising preventing the input signals from being directly input to the embedded memory if the direct access test mode is not selected.

10. The method of claim 8, wherein the checking comprises checking, in response to a reset signal, whether the direct access test mode is selected.