Device for indicating the fixability of a logic circuit

• US 6,185,709 B1
• Filed: 06/30/1998
• Issued: 02/06/2001
• Est. Priority Date: 06/30/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kho, Rex Ngo, Noel, Leo Armand, Dreibelbis, Jeffrey Harris
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/108,069
• Time in Patent Office: 952 Days
• Field of Search: 714/726, 714/727, 714/729, 714/733, 365/200, 365/201, 365/FOR.131, 365/FOR.132, 365/FOR.134
• US Class Current: 714/726
• CPC Class Codes: G11C 29/32 Serial access; Scan testing
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair

Abstract

A device for testing the fixability of logic circuits having an embedded memory. The logic circuit includes a built-in test circuit for generating data which tests the embedded memory. An allocation logic circuit provides an output line for each bit of the memory identifying if the bit has either failed or passed. A Failed Data Bit Register is connected to the output lines. The Failed Data Bit Register includes a plurality of shift register stages. A multiplex circuit associated with each stage of the shift register receives as a first input the corresponding output line of the allocation logic circuit. A second input of the multiplex circuit connects to the preceding stage of the shift register. A clock cycle counter connects to an enabling line of the multiplex circuits and to a source of clock pulses. The clock cycle counter enables the plurality of multiplex circuits to cycle data from the allocation logic circuit through the plurality of stages until it is completely cycled through the plurality of stages. A fail counter is connected to the last stage and counts the number of times Failed Data Bits have been produced by recycling the data.

Claims

1. A device for testing the fixability of a logic circuit tested using a test circuit which provides a known stimulus to the logic circuit and records the response thereto in a shift register comprising:

a plurality of multiplexer circuits, each multiplexer circuit having an output connected to one of a plurality of stages of said shift register, said stages forming a failed data bit register, said multiplexer circuits having a first input connected to receive a failed data bit from said test circuit indicating a circuit failure, and a second input connected to an output of a previous stage, a last of said stages providing an input to the second input of the multiplexer circuit of a first stage;

a counter for enabling said multiplexer circuits to circulate the contents of said stages whereby failed data bits are produced from said last stage indicating a number of failures in said logic circuit; and

means for counting said data bits produced by said last stage.

2. The device according to claim 1 wherein said means for counting said failed data bits produces an output flag indicating the relationship between the number of defective memory cells and a number of replacement memory cells of an embedded memory in said logic circuit.

3. The device according to claim 2 wherein said counter for enabling said multiplexer circuit is enabled by an end of test flag produced by a built in test circuit.

4. The device according to claim 2 whereby said counter for enabling said multiplexer circuits applies clock pulses to said multiplexer circuits following receipt of said end of test flag for circulating said failed data bits in said register stages.

5. The device according to claim 1 wherein said stages constitute a subset of a level sensitive scannable register.

6. A device for testing the fixability of logic circuits having an embedded memory comprising:

a built in test circuit for generating data for testing said memory;

an allocation logic circuit which provides an output line for each bit of said memory identifying said bit as either failed or passed;

a Failed Data Bit Register connected to receive each of said output lines comprising;

a level sensitive scannable register (LSSD) having a plurality of stages;

a plurality of multiplexer circuits one of each being associated with each stage, having a first input, a second input, an enable input and an output, the output of each multiplexer being connected to an input of a respective stage, said first input receiving one of said allocation logic circuit output lines, the second input connected to a preceding shift register stage output, the output of a last of said plurality of stages being connected to the second input of a multiplexer connected to a first of said stages;

a counter connected to each enable input and to a source of clock pulses, said counter enabling said plurality of multiplexer circuits to cycle data from said allocation logic circuit through said plurality of stages until said data is completely cycled through said plurality of stages; and

a fail counter for counting the number of times fail data bits are produced by said last of said stages.

7. The device according to claim 6, wherein said fail counter provides an output when the number of Fail Data Bits exceeds a first predetermined number to indicate that the number of failed memory cells exceeds the number of spare memory cells which may be used to replace failed memory cells.

8. The device according to claim 7, wherein said predetermined number represents the number of redundant data bits of said memory.

9. The device according to claim 6, wherein said counter for enabling said multiplexer circuits is enabled by an End-Of-Test flag generated by said built-in test circuit.

10. The device according to claim 6, wherein said plurality of stages equal the width of said memory plus the number of redundant data bits which can be assigned to said memory.

11. A device for testing the fixability of logic circuits having an embedded memory comprising:

a built-in test circuit for generating data for testing said memory;

an allocation logic circuit which provides an output line for each bit of said memory identifying said bit as either failed or passed;

a Failed Data Bit Register connected to receive data from each of said output lines comprising;

a level sensitive scannable register (LSSD) having a plurality of stages which are connected to each other, a portion of said plurality of stages having an input connected to an allocation logic circuit output line through a multiplexer, or an output of a preceding stage, depending on the state of an enable signal applied to said multiplexer; and

counter means connected to enable said multiplexer following an End-Of-Test signal generated by said test circuit;

whereby the contents of said portion of said plurality of stages are serially produced at a last stage of said portion of stages indicating the number of failed bits of said memory.

12. The device according to claim 11 further comprising:

a counter for accumulating the number of failed bits produced by said last stage.

13. The device according to claim 11, wherein said last stage of said portion is connected to the input of a first stage of said portion of stages through a respective multiplexer connected to said first stage.