Chip performance optimization with self programmed built in self test

• US 6,185,712 B1
• Filed: 07/02/1998
• Issued: 02/06/2001
• Est. Priority Date: 07/02/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Wait, Christopher Douglas, Kirihata, Toshiaki
• Primary Examiner(s): Chung, Phung M.
• Application Number:
  US09/109,145
• Time in Patent Office: 950 Days
• Field of Search: 714/732, 714/733, 714/724
• US Class Current: 714/732
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

An integrated circuit (IC) chip wherein a built-in self test determines the IC'"'"'s optimum electrical performance. A corresponding optimum performance setting is stored in NVRAM on the chip. Upon each chip power-up, the optimum performance setting is retrieved and provided to chip control which sets the chip for its best performance.

Claims

1. An integrated circuit chip, comprising:

a circuit;

a Self Programmable Built In Self Test (SPBIST) logic connected to test said circuit, said SPBIST testing said circuit to determine an optimum performance parameter of said circuit;

control logic providing control parameters for controlling operation of said circuit; and

a non-volatile storage for storing the optimum performance parameter of said circuit as determined by said SPBIST, said non-volatile storage automatically providing the optimum performance parameter to said control logic during a subsequent power up of said circuit, said control logic controlling said circuit so that said circuit operates based on the optimum performance parameter.

2. The integrated circuit chip of claim 1, further comprising:

means for selectively coupling said control logic to said SPBIST or said non-volatile storage responsive to whether said SPBIST is testing said circuit.

3. The integrated circuit chip of claim 2, wherein the optimum performance parameter is an internal voltage level of said circuit.

4. The integrated circuit chip of claim 2, wherein the optimum performance parameter is an internal timing of said circuit.

5. The integrated circuit chip of claim 2, wherein said circuit is a memory array.

6. The integrated circuit chip of claim 5 wherein said memory array is a dynamic random access memory (DRAM) array.

7. The integrated circuit chip of claim 6, wherein the optimum performance parameter controls redundancy of said DRAM.

8. The integrated circuit chip of claim 2, wherein SPBIST does not test said circuit during said subsequent power up.

9. A Dynamic Random Access Memory (DRAM), comprising:

a DRAM core;

Self Programmable Built In Self Test (SPBIST) logic connected to test said DRAM core, said SPBIST testing said DRAM core to determine an optimum performance parameter of said DRAM core;

control logic providing control parameters for controlling operation of said DRAM core; and

a non-volatile storage for storing the optimum performance parameter of said DRAM core as determined by said SPBIST, said non-volatile storage automatically providing the optimum performance parameter to said control logic during a subsequent power up of said circuit, said control logic controlling said DRAM core so that said DRAM core operates based on the optimum performance parameter.

10. The DRAM of claim 9, further comprising:

means for selectively coupling said control logic to said SPBIST or said non-volatile storage responsive to whether said SPBIST is testing said DRAM core.

11. The DRAM of claim 10, wherein the optimum performance parameter is an internal voltage level of said DRAM core.

12. The DRAM of claim 10, wherein the optimum performance parameter is an internal timing of said DRAM core.

13. The DRAM of claim 10, wherein the optimum performance parameter controls redundancy of said DRAM core.

14. An integrated circuit chip comprising:

a circuit core;

Built In Self Test (BIST) logic connected to test and control said circuit core during a test condition;

control logic providing control parameters to said circuit core responsive to said BIST logic during said test condition; and

non-volatile storage receiving control information from said BIST logic during said test condition and providing control information to said control logic during a normal power up.

15. A method for tuning an integrated circuit chip for optimum performance, comprising:

testing a circuit on the chip to determine an optimum performance parameter of the circuit;

storing the optimum performance parameter in a memory on the chip;

supplying power to the chip; and

setting the circuit to operate based on the optimum performance parameter stored in said memory, said setting step being automatically performed in response to said power supplying step.

16. The method of claim 15, wherein the circuit is a Dynamic Random Access Memory core and the optimum performance parameter sets sense amplifier timing.

17. The method of claim 16 wherein the testing step is a built in self test.

18. The method of claim 15, wherein said testing step includes:

inputting a first test condition into the circuit;

determining an initial performance result of the circuit based on the first test condition; and

if said initial performance result does not exceed the predetermined limit, performing the following steps;

(a) incrementing the test condition,

(b) inputting the incremented test condition into the circuit,

(c) determining a performance result of the circuit based on the incremented test condition, and

(d) if the performance result determined in step (c) exceeds the predetermined limit, storing the incremented test condition into said memory as the optimum performance parameter, and if the performance result in step (c) does not exceed the predetermined limit, repeating steps (a)-(d).

19. The method of claim 15, wherein the optimum performance parameter includes one of an internal operating voltage of the circuit, an internal timing of the circuit, and redundancy.

20. The method of claim 15, wherein the circuit is not tested to determine said optimum performance subsequent to said power supplying step.

21. A method for controlling operation of a DRAM, comprising:

testing a sense amplifier circuit of the DRAM to determine an optimum delay time for setting the sense amplifier;

storing the optimum delay time in a memory on the chip;

supplying power to the chip; and

setting the sense amplifier circuit to operate based on the optimum delay time stored in said memory, said setting step being automatically performed in response to said power supplying step.

22. The method of claim 21, wherein said testing step includes:

inputting a first reference voltage into a timing delay circuit of the sense amplifier circuit;

determining an initial delay time of the sense amplifier circuit based on the first reference voltage;

if the initial delay time does not coincide with a desired value, performing the following steps;

(a) incrementing the first reference voltage,

(b) inputting the incremented reference voltage into the circuit,

(c) determining a delay time of the sense amplifier circuit based on the incremented reference voltage, and

(d) if the delay time determined in step (c) matches the desired value, storing the incremented reference voltage into said memory as the optimum delay time, and if the performance result in step (c) does not match the desired value, repeating steps (a)-(d).