Dual detector read channel with semi-soft detection

• US 6,185,716 B1
• Filed: 01/30/1998
• Issued: 02/06/2001
• Est. Priority Date: 01/30/1998
• Status: Expired due to Term

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Inventors: Riggle, C. Michael
• Primary Examiner(s): De Cady, Albert
• Assistant Examiner(s): LAMARRE, GUY J
• Application Number:
  US09/016,550
• Time in Patent Office: 1,103 Days
• Field of Search: 714/769, 360/46, 360/65, 364/488, 364/825, 341/59, 375/233, 708/323
• US Class Current: 714/769
• CPC Class Codes: G11B 20/10009 Improvement or modification of read or write signals

Abstract

An apparatus for detecting data within a signal having both data and noise is disclosed herein. The apparatus includes means for receiving first samples of an input signal, a first detection unit and a second detection unit. The first detection unit processes the first data samples to create a first bit signal, a second bit signal and a probability related signal. The second detection unit includes first and second modification units and a selection unit. The first and second modification units separately modify the first data samples based on the first and second bit signals, respectively, to create first and second error signals, respectively. The selection unit selects one of the first and second bit signals based on the first and second error signals and a threshold signal.

Claims

1. An apparatus for detecting data within a signal having both data and noise, said apparatus for use in a data storage system, comprising:

means for receiving first data samples of an input signal;

a first detection unit for processing said first data samples to create a first bit signal, a second bit signal, and a probability related signal;

first and second modification units for separately modifying said first data samples based on said first and second bit signals, respectively, to create first and second error signals, respectively; and

a selection unit for selecting one of said first or second bit signals based on said first and second error signals and a threshold signal.

2. The apparatus of claim 1, further comprising:

a multiplexer for processing said signal selected by said selection unit.

3. The apparatus of claim 1, wherein:

said first and second modification units include first and second cancellers respectively, for subtracting cancellation values from said first data samples.

4. The apparatus of claim 3, wherein:

said first and second cancellers include a random access memory (RAM) for storing said cancellation values.

5. The apparatus of claim 1, wherein:

said first and second error signals are squared error sums that are accumulated over a predetermined number of bit times.

6. The apparatus of claim 1, wherein:

said selection unit includes a subtracter for determining a difference between said first and second error signals.

7. The apparatus of claim 6, wherein:

said selection unit includes a comparator for comparing said difference to said probability related signal.

8. The apparatus of claim 1, wherein:

said first detection unit includes a pair of decision feedback equalizers.

9. The apparatus of claim 1, wherein:

said first bit signal and said second bit signal represent two possible detected data strings for the first data samples.

10. The apparatus of claim 1, wherein:

said threshold signal is calculated using said probability related signal.

11. The apparatus of claim 10, wherein:

said probability related signal is approximately proportional to a log likelihood that bits of the first bit signal are accurate.