Chip scale packages and methods for manufacturing the chip scale packages at wafer level

• US 6,187,615 B1
• Filed: 12/28/1998
• Issued: 02/13/2001
• Est. Priority Date: 08/28/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jang, Dong Hyeon, Kim, Nam Seog, Kwon, Heung Kyu, Kang, Sa Yoon
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/222,250
• Time in Patent Office: 778 Days
• Field of Search: 257/737, 257/738, 438/113, 438/613, 438/108, 438/778
• US Class Current: 438/113
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/1132 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

In accordance with the present invention, a chip scale package (CSP) is manufactured at wafer-level. The CSP includes a chip, a conductor layer for redistribution of the chip pads of the chip, one or two insulation layers and multiple bumps, which are interconnected to respective chip pads by the conductor layer and are the terminals of the CSP. In addition, in order to improve the reliability of the CSP, a reinforcing layer, an edge protection layer and a chip protection layer is provided. The reinforcing layer absorbs stress applied to the bumps when the CSP are mounted on a circuit board and used for an extended period, and extends the life of the bumps, and thus, the life of the CSP. The edge protection layer and the chip protection layer prevent external force from damaging the CSP. After forming all elements constituting the CSP on the semiconductor wafer, the semiconductor wafer is sawed to produce individual CSPs.

Claims

1. A method for manufacturing a semiconductor package, comprising:

providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor circuit chip having a plurality of chip pads and a passivation layer thereon;

forming a patterned conductor layer directly on the passivation layer;

forming an insulation layer on the patterned conductor layer;

forming a plurality of external terminals of the semiconductor package; and

sawing the wafer to separate the semiconductor integrated circuit chips, wherein the patterned conductor layer connects the chip pads to respective external terminals, and the insulation layer includes a plurality of openings through which the external terminals connect to the patterned conductor layer.

2. The method of claim 1, wherein forming the external terminals comprises:

placing solder balls at the openings in the insulation layer so that each solder ball sits on an associated opening; and

heating the solder balls to reshape the solder balls and attach the solder balls to the patterned conductor layer.

3. The method of claim 1, wherein forming the external terminals comprises:

screen-printing solder paste using a mask having a plurality of mask openings, each of the mask openings corresponding to a respective one of the openings in the insulation layer;

heating the solder paste to form solder bumps attached to bump pads formed in the patterned conductor layer.

4. The method of claim 1, wherein forming the patterned conductor layer comprises screen-printing a conductive paste and curing the paste.

5. The method of claim 1, wherein forming the patterned conductor layer comprises plating a metal layer and etching the metal layer.

6. The method of claim 1, wherein the insulation layer contains a polymeric material that is selected from a group consisting of benzocyclobutene, polyimide and epoxy resin.

7. The method of claim 1, further comprising forming a chip protection layer on a back side of the semiconductor wafer.

8. The method of claim 7, wherein the chip protection layer is formed by a spin-coating method.

9. The method of claim 1, further comprising forming a chip edge protection layer along scribe lines on a top surface of the semiconductor wafer.

10. The method of claim 9, wherein forming the chip edge protection layer comprises dispensing a liquid material on the scribe lines on the wafer.

11. A method for manufacturing a semiconductor package, comprising:

providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor circuit chip having a plurality of chip pads and a passivation layer thereon;

forming a patterned conductor layer directly on the passivation layer;

forming an insulation layer on the patterned conductor layer;

forming a plurality of external terminals of the semiconductor package, wherein the insulation layer includes a plurality of openings through which the external terminals connect to the patterned conductor layer, and the patterned conductor layer connects the chip pads to respective external terminals;

forming a reinforcing layer on the insulation layer, wherein the external terminals are exposed through the reinforcing layer; and

sawing the wafer to separate the semiconductor integrated circuit chips.

12. The method of claim 11, wherein the reinforcing layer is formed of a polymer.

13. The method of claim 12, wherein forming the reinforcing layer comprises dispensing a liquid polymer for the reinforcing layer and curing the polymer.

14. The method of claim 11, wherein the reinforcing layer is below a surface that connects the tips of the external terminals.

15. The method of claim 14, wherein a perpendicular distance from the surface to a point where the reinforcing layer meets the external terminals is about 100 μ

m.

16. A method for manufacturing a semiconductor package, comprising:

providing a semiconductor wafer having a plurality of semiconductor integrated circuit chips and a plurality of scribe lines, each of the semiconductor integrated circuit chips having a plurality of chip pads and a passivation layer thereon;

forming a lower insulation layer on the passivation layer of the semiconductor chip, the lower insulation layer having openings over the chip pads;

forming a patterned conductor layer which connects to the chip pads through the openings in the lower insulation layer;

forming an upper insulation layer on the patterned conductor layer, the upper insulation layer having openings which expose portions of the patterned conductor layer;

forming a plurality of external terminals of the semiconductor package at the openings in the upper insulation layer, the external terminals connecting to the patterned conductor layer, wherein the patterned conductor layer interconnects each of the chip pads to respective external terminals;

forming a reinforcing layer on the upper insulation layer; and

sawing the wafer to separate the semiconductor integrated circuit chips.

17. The method of claim 16, wherein the upper insulation layer contains a polymeric material which is one selected from a group consisting of benzocyclobutene, polyimide and epoxy resin.

18. The method of claim 16, wherein the lower insulation layer contains a polymeric material.

19. The method of claim 16, wherein the polymeric material is selected from a group consisting of benzocyclobutene, polyimide and epoxy resin.

20. The method of claim 16, wherein the lower insulation layer is formed of an inorganic material.