Method to prevent gate oxide damage by post poly definition implantation

• US 6,187,639 B1
• Filed: 04/21/1997
• Issued: 02/13/2001
• Est. Priority Date: 04/21/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Jyh-Haur, Shen, Chih-Heng
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US08/844,629
• Time in Patent Office: 1,394 Days
• Field of Search: 438/301, 438/305, 438/307, 438/585, 438/592, 438/948
• US Class Current: 438/291
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: Y10S 438/948 Radiation resist

Abstract

A method for preventing gate oxide damage caused by post poly definition implantation is disclosed. It is shown that the antenna ratio that is correlatable to oxide damage can be reduced and made to approach zero by implementing a mask layout during ion implantation. This involves covering all of the polysilicon electrodes with a photoresist mask, and reducing the effective antenna ratio to zero, and performing ion implantation to form source/drain regions thereafter. In this manner, the dependency of ion implantation to pattern sensitivity is also removed.

Claims

1. A method for preventing oxide damage comprising the steps of:

providing a substrate having polysilicon electrodes over an oxide layer;

forming photoresist mask completely covering said polysilicon electrodes, wherein said photoresist provides coverage during all ion implantation steps in order to prevent oxide damage during any subsequent ion implantation; and

performing on implantation to form heavily doped source/drain regions in said substrate prior to the removal of said photoresist mask.

2. A method for preventing oxide damage comprising the steps of:

providing a substrate having field oxide regions;

growing gate oxide over said substrate;

performing first ion implantation to adjust threshold voltage;

depositing polysilicon layer over said substrate;

patterning said polysilicon layer;

forming photoresist mask completely covering said polysilicon electrodes, wherein said photoresist provides coverage during all subsequent ion implantation steps in order to prevent oxide damage during any subsequent ion implantation; and

performing a second ion to form heavily doped source/drain regions in said substrate prior to the removal of said photoresist mask.

3. The method of claim 2, wherein said substrate is silicon.

4. The method of claim 2, wherein said gate oxide has a thickness between about 5 to 20 nanometers (nm).

5. The method of claim 2, wherein said first ion implantation is accomplished with boron-fluoride ions.

6. The method of claim 2, wherein said first ion implantation has a dose between about 1×

10¹² to 5×

10¹² ions/cm².

7. The method of claim 2, wherein said first ion implantation is accomplished with energy between about 25 to 80 keV.

8. The method of claim 2, wherein said polysilicon layer has a thickness between about 100 to 300 nm.

9. The method of claim 2, wherein said photoresist mask has a thickness between about 1 to 2 μ

m.

10. The method of claim 2, wherein said second ion implantation is accomplished with As ions.

11. The method of claim 2, wherein said second ion implantation is accomplished with a dose between about 1×

10¹⁵ to 5×

10¹⁵ ions/cm².

12. The method of claim 2, wherein said second ion implantation is accomplished at an energy between about 30 to 70 keV.