Multi-stage method for forming optimized semiconductor seed layers

• US 6,187,670 B1
• Filed: 12/02/1998
• Issued: 02/13/2001
• Est. Priority Date: 12/02/1998
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Brown, Dirk, Iacoponi, John A.
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US09/204,741
• Time in Patent Office: 804 Days
• Field of Search: 438/688, 438/687, 438/685, 438/680, 438/681, 438/638, 438/640, 438/701, 438/686
• US Class Current: 438/638
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 2221/1089 Stacks of seed layers

Abstract

A method is provided for forming seed layers in semiconductor channel and via openings by using a two-stage approach after lining the channel and via openings with barrier material. First, a low temperature deposition of a seed layer is performed at below the 250° C. at which conductive material agglomeration occurs. Second, a higher temperature deposition of a seed layer is performed at above 250° C. Then, the conductive material is deposited to fill the channel and via openings.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor substrate with a dielectric layer formed thereon, wherein said dielectric layer overlays a region on said semiconductor substrate;

forming an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a portion of said region on said semiconductor substrate;

forming a barrier layer on said dielectric layer and in said opening, including along said walls, in contact with said region of said semiconductor substrate, said barrier layer formed to a thickness insufficient to fill said opening, wherein said step of forming said barrier layer is performed by a process selected from a group comprising physical vapor deposition, chemical vapor deposition, and a combination thereof;

forming a first seed layer in contact with said barrier layer, said seed layer formed to a thickness insufficient to fill said opening, wherein said step of forming said seed layer is performed by a deposition process at first temperature, wherein said step of forming said first seed layer by said first temperature deposition increases conformality of said first seed layer, conformality is defined to be A/C, where A is the thickness of the thinnest area of said seed layer along said walls and C is the thickness of the thickest area of said seed layer along said walls;

forming a second seed layer in contact with said first seed layer, said second seed layer formed to a thickness insufficient to fill said opening, wherein said step of forming said second seed layer is performed by a deposition process at a second temperature above said first temperature, wherein said step of forming said second seed layer by said second temperature deposition increases sidewall step coverage, side wall step coverage is defined to be A/B, where A is the thickness of the thinnest area of said seed layer along said walls and B is the thickness of said seed layer on said dielectric layer;

forming a conductive layer in contact with said second seed layer, said conductive material layer substantially filling said opening; and

removing said barrier layer said first and second seed layers, and said conductive layer outside of said opening.

2. The method as claimed in claim 1 wherein said steps of:

forming said first seed layer is performed by a sputter deposition process at a temperature below 250°

C.; and

forming said second seed layer is performed by a sputter deposition process at a temperature above 250°

C.

3. The method as claimed in claim 1 wherein said step of:

forming said first seed layer is performed by said sputter deposition process below 150°

C.; and

forming said second seed layer is performed by said sputter deposition process above 250°

C.

4. The method as claimed in claim 1 wherein said step of:

forming said first seed layer is performed by said sputter deposition process below 100°

C.; and

forming said second seed layer is performed by said sputter deposition process above 250°

C.

5. The method as claimed in claim 1 wherein said step of:

forming said first seed layer begins below a temperature of 250°

C. and increases continuously into forming said second seed layer; and

forming said second seed layer ends above a temperature of 250°

C.

6. The method as claimed in claim 1 wherein said step of:

forming said first seed layer begins below a temperature of 100°

C. and increases rapidly and continuously into forming said second seed layer; and

forming said second seed layer ends above a temperature of 250°

C.

7. The method as claimed in claim 1 wherein said step of forming said barrier layer is performed with a material selected from a group comprising tantalum, titanium, tungsten, a nitride thereof, an alloy thereof, and a combination thereof.

8. The method as claimed in claim 1 wherein said step of forming said seed layer is performed with a material selected from a group comprising copper, aluminum, gold silver, a compound thereof, an alloy thereof, and a combination thereof.

9. A method of manufacturing a semiconductor device, comprising the steps of:

providing a semiconductor substrate with a dielectric layer formed thereon, wherein said dielectric layer overlays a region on said semiconductor substrate;

forming an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a portion of said region on said semiconductor substrate;

forming a barrier layer comprising a material selected from the group consisting of titanium and tantalum on said dielectric layer and in said opening, including along said walls, in contact with said region of said semiconductor substrate, said barrier layer formed to a thickness insufficient to fill said opening, wherein said step of forming said adhesion layer is performed by a process selected from a group comprising physical vapor deposition, chemical vapor deposition, and a combination thereof;

forming a seed layer comprising a material selected from the group consisting of copper, gold, silver, a compound thereof, and a combination thereof in contact with said barrier layer, said seed layer formed to a thickness insufficient to fill said opening, wherein said step of forming said seed layer is performed by sputter deposition around and below 100°

C. to prevent agglomeration and to reduce its thickness at least on top of said dielectric layer and around an upper portion of said walls, wherein said step of forming said seed layer increases sidewall step coverage and conformality of said seed layer, sidewall step coverage is defined to be A/B and conformality is defined to be A/C, where A is the thickness of the thinnest area of said seed layer along said walls, B is the thickness of said seed layer on said dielectric layer, and C is the thickness of the thickest area of said seed layer along said walls; and

forming a conductive layer in contact with said seed layer, wherein said conductive material is selected from a group comprising aluminum, tungsten, copper, gold, silver, and a combination thereof said conductive material layer substantially fills said opening, and the step of forming said layer of conductive material is performed by a process selected from a group comprising physical vapor deposition, chemical vapor deposition, electroplating, and a combination thereof.

10. The method as claimed in claim 9 wherein said step of

forming said seed layer is performed in part by said sputter deposition process above 250° C.