Interconnect with low dielectric constant insulators for semiconductor integrated circuit manufacturing

• US 6,187,672 B1
• Filed: 09/22/1998
• Issued: 02/13/2001
• Est. Priority Date: 09/22/1998
• Status: Expired due to Term

• Current Assignee: Newport Fab, LLC (Tower Semiconductor Limited)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Zhao, Bin, Brongo, Maureen R.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Davis, Jamie L.
• Application Number:
  US09/158,337
• Time in Patent Office: 875 Days
• Field of Search: 438/623, 438/624, 438/627, 438/628, 438/629, 438/631, 438/633, 438/634, 438/637, 438/639, 438/618, 438/622, 438/626, 438/778, 438/780
• US Class Current: 438/639
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76819 Smoothing of the dielectric planarisation of insulating materials per se H01L21/31051
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence

Abstract

A method is provided for forming an improved interconnect structure on a semiconductor body. A first metal layer is deposited on the semiconductor body. A sacrificial layer having a height is deposited on the first metal layer. The sacrificial layer and the metal layer are patterned to form separate metal lines with the sacrificial layer remaining on said metal lines. A low-k material is then deposited to fill the gaps between metal lines and to cover the sacrificial layer. The low-k material is then removed to a level within the height of the sacrificial layer. The sacrificial layer is then removed. A protective layer is deposited on top of the metal lines and the low-k material. A dielectric layer is deposited over the protective layer. The protective layer protects the low-k material from attack by chemicals utilized by subsequent process steps to etch vias in the dielectric layer, to strip photo-resist, and to clean the vias. The protective layer is then selectively etched away to make contact between a via plug and the metal lines.

Claims

1. A method for forming an interconnect structure on a semiconductor body, comprising the steps of:

(a) depositing a first metal layer on a semiconductor body;

(b) depositing a sacrificial layer on the first metal layer, said sacrificial layer having a height;

(c) patterning the sacrificial layer and the first metal layer to form separate metal lines with a sacrificial layer cap on said metal lines;

(d) depositing a low-k material to fill gaps between said metal lines and to cover the sacrificial layer;

(e) removing the low-k material to a level within the height of the sacrificial layer;

(f) removing the sacrificial layer;

(g) depositing a protective layer to cover the metal lines and the low-k material

(h) depositing an insulator on the protective layer;

depositing and patterning a photoresist layer on the insulator;

(i) creating vias in the insulator;

(j) performing a photoresist strip;

(k) performing a set clean; and

(l) selectively etching the protective layer using an anisotropic etch configured to leave a spacer on a vertical portion of the low-k material in the vias.

2. The method of claim 1, wherein the step of removing the low-k material to a level within the height of the sacrificial layer includes the step of etching back the low-k material to a level within the height of the sacrificial layer.

3. The method of claim 2 wherein step of etching back the low-k material to a level within the height of the sacrificial layer includes a plasma etch step.

4. The method of claim 1, wherein the step of removing the low-k material to a level within the height of the sacrificial layer includes the step of polishing the low-k material to a level within the height of the sacrificial layer.

5. The method of claim 4, wherein the step of polishing the low-k material to a level within the height of the sacrificial layer includes a chemical mechanical polish (CMP) step.

6. The method of claim 1, wherein the step of removing the low-k material to a level within the height of the sacrificial layer includes the steps of polishing the low-k material and etching back the low-k material.

7. The method of claim 6, wherein the steps of polishing the low-k material and etching back the low-k material includes a plasma etch step and a chemical mechanical polish (CMP) step.

8. The method of claim 1, wherein selectively etching the protective layer further includes the step of utilizing an isotropic etch.

9. The method of claim 1, further comprising filling the vias with a metal.

10. The method of claim 9, further comprising depositing and patterning a second metal layer over the insulator.

11. The method of claim 10, wherein the sacrificial layer is made of a material selected from the group consisting of an oxide, silicon oxide, aluminum oxide, silicon nitride, silicon carbide, a polymer, an organic material, a conductive material, titanium, titanium nitride, tungsten, tungsten nitride, and poly-silicon.

12. The method of claim 1, further comprising the steps of

depositing a second metal layer onto the insulator and into the vias; and

patterning and etching the second metal layer to form conductive features.