High density MOS-gated power device and process for forming same

• US 6,188,105 B1
• Filed: 04/01/1999
• Issued: 02/13/2001
• Est. Priority Date: 04/01/1999
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Zeng, Jun, Kocon, Christopher B.
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/283,531
• Time in Patent Office: 684 Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A high density MOS-gated device comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a heavily doped source region of the first conduction type and a doped well region of a second and opposite conduction type at an upper surface. The upper surface, which comprises a contact area for the source region, further includes a recessed portion that comprises a contact area for a heavily doped deep body region of the second conduction type in the upper layer underlying the recessed portion. The device further includes a trench gate disposed in the upper layer and comprising a conductive material separated from the upper layer by an insulating layer. A process for forming a high density MOS-gated device comprises providing a semiconductor substrate comprising a doped upper layer of a first conduction type. A doped well region of a second and opposite conduction type is formed in an upper surface of the upper layer, and a dopant of the first conduction type is implanted in the well region to form a heavily doped source region. A layer of nitride is formed on the upper surface of the upper layer, and the nitride layer and upper layer are selectively etched, thereby forming a trench in the upper layer. The trench is lined with an insulating layer, then filled with a conductive material to form a trench gate. The nitride layer is removed, and a layer of interlevel dielectric material is formed on the trench gate and the upper surface of the upper layer. The interlevel dielectric layer is selectively etched, thereby forming a source region contact area. The source region is selectively etched to form a shallow recess that provides a body region contact area. A dopant of the second conduction type is implanted into the recess, thereby forming a deep body region underlying the recess.

Claims

1. A high density MOS-gated device comprising:

a semiconductor substrate;

a doped upper layer of a first conduction type disposed on said substrate, said upper layer comprising a heavily doped source region of said first conduction type and a doped well region of a second and opposite conduction type at an upper surface of said upper layer, said upper surface comprising a contact area for said source region, said upper surface further comprising a recessed portion comprising a contact area for a heavily doped deep body region of said second conduction type in said upper layer, said deep body region underlying said recessed portion; and

a trench gate disposed in said upper layer, said gate comprises a conductive material separated from said upper layer by an insulating layer.

2. The device of claim 1 further comprising a shallow body region underlying said source region contact area.

3. The device of claim 1 further comprising a metal contact on said source region contact area and on said body region contact area in said recessed portion in said upper surface of said upper layer.

4. The device of claim 1 wherein said upper layer is included within said substrate.

5. The device of claim 1 wherein said upper layer comprises an epitaxial layer.

6. The device of claim 1 wherein said first conduction type is N and said second conduction type is P.

7. The device of claim 1 wherein said substrate comprises monocrystalline silicon and said insulating layer comprises silicon dioxide.

8. The device of claim 1 wherein said conductive material in said trench gate comprises highly doped polysilicon.

9. The device of claim 1 wherein said interlevel dielectric material is borophosphosilicate glass or phosphosilicate glass.

10. The device of claim 1 wherein said body contact area is smaller than said source contact area.

11. The device of claim 1 selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.

12. A process for forming a high density MOS-gated device, said process comprising:

providing a semiconductor substrate comprising a doped upper layer of a first conduction type, said upper layer having an upper surface;

forming a doped well region of a second and opposite conduction type in said upper surface of said upper layer;

implanting a dopant of said first conduction type in said well region, thereby forming a heavily doped source region in said well region;

forming a layer of nitride on said upper surface of said upper layer;

selectively etching said nitride layer and said upper layer, thereby forming a trench in said upper layer;

lining said trench with an insulating layer, then filling said trench with a conductive material, thereby forming a trench gate;

removing said nitride layer and forming a layer of interlevel dielectric material on said trench gate and said upper surface of said upper layer;

selectively etching said interlevel dielectric layer, thereby forming a source region contact area;

selectively etching said source region, thereby forming a shallow recess in said source region, said recess comprising a body region contact area; and

implanting a dopant of said second conduction type into said recess, thereby forming a deep body region underlying said recess.

13. The process of claim 12 further comprising:

forming a screen layer of oxide on said upper surface of said upper layer prior to forming said nitride layer.

14. The process of claim 12 further comprising:

implanting a dopant of said second conduction type into said source region contact area, thereby forming a shallow body region underlying said source region contact area.

15. The process of claim 12 further comprising:

forming a metal contact on said source region contact area and on said body region contact area.

16. The process of claim 12 wherein said upper layer is included within said substrate.

17. The process of claim 12 wherein said upper layer comprises an epitaxial layer.

18. The process of claim 12 wherein said first conduction type is N and said second conduction type is P.

19. The process of claim 12 wherein said substrate comprises monocrystalline silicon and said insulating layer comprises silicon dioxide.

20. The process of claim 12 wherein said conductive material in said trench gate comprises highly doped polysilicon.

21. The process of claim 12 wherein said dopant of a first conduction type comprises arsenic or phosphorus.

22. The process of claim 12 wherein said dopant of a second conduction type comprises boron.

23. The process of claim 12 wherein said interlevel dielectric material comprises borophosphosilicate glass or phosphosilicate glass.

24. The process of claim 12 wherein said body contact area is smaller than said source contact area.

25. The process of claim 12 wherein said device is selected from the group consisting of a power MOSFET, an insulated gate bipolar transistor, and an MOS-controlled thyristor.

26. In an improved process for forming a high density MOS-gated device including the steps of forming a gate trench in an upper layer of a substrate, forming a well region in the upper layer, implanting a dopant of a first conduction type into the well region to form a source region in the well region adjacent to the gate trench, the improvement comprising:

selectively etching a portion of the source region, thereby forming a recess comprising a body region contact area, the unetched portion of said source region comprising a source region contact area; and

implanting a dopant of a second conduction type into the recess, thereby forming a deep body region underlying said recess.

27. The process of claim 26 further comprising:

implanting a dopant of said second conduction type into said source region contact area, thereby forming a shallow body region underlying said source region contact area.

28. The process of claim 26 further comprising:

forming a metal contact on said source region contact area and on said body region contact area.

29. The process of claim 26 wherein said upper layer is included within said substrate.

30. The process of claim 26 wherein said upper layer comprises an epitaxial layer.

31. The process of claim 26 wherein said first conduction type is N and said second conduction type is P.

32. The process of claim 26 wherein said substrate comprises monocrystalline silicon and said insulating layer comprises silicon dioxide.

33. The process of claim 26 wherein said conductive material in said trench gate comprises highly doped polysilicon.

34. The process of claim 26 wherein said body contact area is smaller than said source contact area.