Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response

• US 6,188,211 B1
• Filed: 05/11/1999
• Issued: 02/13/2001
• Est. Priority Date: 05/13/1998
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Rincon-Mora, Gabriel Alfonso, Corsi, Marco
• Primary Examiner(s): BERHANE, ADOLF D
• Application Number:
  US09/309,991
• Time in Patent Office: 644 Days
• Field of Search: 323/273, 323/277, 323/280, 323/281, 323/313, 323/315
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: G05F 3/247 producing a voltage or current as a predetermined function of the supply voltage
• CPC Class Codes: G05F 3/267 using both bipolar and field-effect technology

Abstract

A low drop-out (LDO) voltage regulator (10) and system (100) including the same are disclosed. An error amplifier (38) controls the gate voltage of a source follower transistor (24) in response to the difference between a feedback voltage (V_FB) from the output (V_OUT) and a reference voltage (V_REF). The source of the source follower transistor (24) is connected to the gates of an output transistor (12), which drives the output (V_OUT) from the input voltage (V_IN) in response to the source follower transistor (24). A current mirror transistor (14) has its gate also connected to the gate of the output transistor (12), and mirrors the output current at a much reduced ratio. The mirror current is conducted through network of transistors (18, 22), and controls the conduction of a first feedback transistor (28) and a second feedback transistor (35) which are each connected to the source of the source follower transistor (24) and in parallel with a weak current source (34). The response of the first feedback transistor (28) is slowed by a resistor (32) and capacitor (30), while the second feedback transistor (35) is not delayed. As such, the second feedback transistor (35) assists transient response, particularly in discharging the gate capacitance of the output transistor (12), while the first feedback transistor (28) partially cancels load regulation effects.

Claims

1. A voltage regulator circuit, comprising:

an error amplifier, having a first input receiving a reference voltage and having a second input, for generating a voltage at an output responsive to a difference in the voltages at its first and second inputs;

a source follower transistor having a gate coupled to the output of the error amplifier, having a drain connected to an input voltage, and having a source;

a current source, coupled between the source of the source follower transistor and a reference bias voltage;

an output leg, comprising an output MOS transistor having a source-drain path coupled between the input voltage and an output node, and having a gate coupled to the source of the source follower transistor;

a mirror leg, comprising a mirror MOS transistor having a source-drain path coupled on one side to the input voltage, and having a gate coupled to the source of the source follower transistor;

a negative feedback circuit coupled to the output node and to the second input of the error amplifier, for providing feedback to the error amplifier based upon the voltage at the output node;

a first positive feedback transistor having a conduction path connected in parallel with the current source, having a control electrode coupled to the mirror leg;

a delay network, coupled to the control electrode of the first positive feedback transistor, for delaying the response of the control electrode of the first positive feedback transistor; and

a second positive feedback transistor, having a conduction path connected in parallel with the current source, and having a control electrode coupled to the mirror leg, the second positive feedback transistor having a faster response than the first positive feedback transistor.

2. The voltage regulator of claim 1, wherein the delay network comprises:

a resistor, connected on one side to the control electrode of the first positive feedback transistor, and connected on a second side to the mirror leg; and

a capacitor, connected on one side to the control electrode of the first positive feedback transistor, and connected on a second side to a fixed voltage.

3. The voltage regulator of claim 1, wherein the output leg further comprises:

a first bipolar transistor having a collector-emitter path connected on one end to the output node, and having a base connected to another end of the collector-emitter path; and

a first MOS transistor having a source-drain path coupled between the collector-emitter path of the first bipolar transistor and the reference bias voltage, and having a gate;

and wherein the mirror leg further comprises;

a second bipolar transistor having a collector-emitter path connected on one end to a second side of the source-drain path of the mirror MOS transistor, and having a base connected to the base of the first bipolar transistor; and

a second MOS transistor having a source-drain path coupled between the collector-emitter path of the second bipolar transistor and the reference bias voltage, and having a gate connected to the gate of the first MOS transistor and to the collector-emitter path of the second bipolar transistor.

4. The voltage regulator of claim 3, wherein the control electrode of the first positive feedback transistor and the control electrode of the second positive feedback transistor are coupled to the mirror leg at a node connecting the source-drain path of the second MOS transistor and the collector-emitter path of the second bipolar transistor.

5. The voltage regulator of claim 4, wherein the delay network comprises:

a resistor, connected on one side to the control electrode of the first positive feedback transistor, and connected on a second side to the node connecting the source-drain path of the second MOS transistor and the collector-emitter path of the second bipolar transistor; and

a capacitor, connected on one side to the control electrode of the first positive feedback transistor, and connected on a second side to a fixed voltage.

6. The voltage regulator of claim 1, wherein the source follower transistor, and the first and second positive feedback transistors, are each an n-channel MOS transistor.

7. The voltage regulator of claim 6, wherein the mirror MOS transistor and the output MOS transistor are each a p-channel MOS transistor.

8. The voltage regulator of claim 1, wherein the negative feedback circuit comprises a voltage divider.

9. A method of generating a regulated output voltage from an input voltage, comprising:

comparing a feedback voltage based upon the output voltage to a reference voltage;

responsive to the comparing step determining that the feedback voltage is lower than the reference voltage, controlling conduction through a source follower transistor having a drain coupled to the input voltage, and having a source coupled to the gate of an output transistor, so that the output transistor increases the current conducted through a source-drain path connected between the input voltage and an output node;

mirroring the current conducted by the output transistor with a mirror transistor;

responsive to an increase in the mirrored current, turning on a first transistor connected between the source of the source follower transistor and a reference bias voltage, to assist in discharge of the gate of the output transistor; and

after the turning on step, turning on a second transistor connected between the source of the source follower transistor and the reference bias voltage.

10. The method of claim 9, further comprising:

delaying the step of turning on a second transistor with a resistor-capacitor network.

11. The method of claim 9, further comprising:

generating the feedback voltage using a resistor divider.

12. The method of claim 9, further comprising:

responsive to the comparing step determining that the feedback voltage is higher than the reference voltage, controlling conduction through the source follower transistor so that the output transistor decreases the current conducted through its source-drain path; and

responsive to a decrease in the mirrored current, turning off the first and second transistors.

13. An electronic system, comprising:

a voltage source;

a reference voltage generator circuit;

a load; and

a voltage regulator, comprising;

an error amplifier, having a first input receiving a reference voltage from the reference voltage generator circuit and having a second input, for generating a voltage at an output responsive to a difference in the voltages at its first and second inputs;

a source follower transistor having a gate coupled to the output of the error amplifier, having a drain connected to an input voltage from the voltage source, and having a source;

a current source, coupled between the source of the source follower transistor and a reference bias voltage;

an output leg, comprising an output MOS transistor having a source-drain path coupled between the input voltage and an output node coupled to the load, and having a gate coupled to the source of the source follower transistor;

a mirror leg, comprising a mirror MOS transistor having a source-drain path coupled on one side to the input voltage, and having a gate coupled to the source of the source follower transistor;

a negative feedback circuit coupled to the output node and to the second input of the error amplifier, for providing feedback to the error amplifier based upon the voltage at the output node;

a first positive feedback transistor having a conduction path connected in parallel with the current source, having a control electrode coupled to the mirror leg;

a delay network, coupled to the control electrode of the first positive feedback transistor, for delaying the response of the control electrode of the first positive feedback transistor; and

a second positive feedback transistor, having a conduction path connected in parallel with the current source, and having a control electrode coupled to the mirror leg, the second positive feedback transistor having a faster response than the first positive feedback transistor.

14. The system of claim 13, wherein the voltage source comprises a battery.

15. The system of claim 14, wherein the voltage source further comprises a DC-DC converter, having an input coupled to the battery and having an output coupled to the voltage regulator.

16. The system of claim 15, wherein the DC-DC converter, the voltage reference generator circuit, and the voltage regulator are implemented within a single integrated circuit.

17. The system of claim 13, wherein the load comprises analog circuitry.

18. The system of claim 13, wherein the output leg further comprises:

a first bipolar transistor having a collector-emitter path connected on one end to the output node, and having a base connected to another end of the collector-emitter path; and

a first MOS transistor having a source-drain path coupled between the collector-emitter path of the first bipolar transistor and the reference bias voltage, and having a gate;

and wherein the mirror leg further comprises;

a second bipolar transistor having a collector-emitter path connected on one end to a second side of the source-drain path of the mirror MOS transistor, and having a base connected to the base of the first bipolar transistor; and

a second MOS transistor having a source-drain path coupled between the collector-emitter path of the second bipolar transistor and the reference bias voltage, and having a gate connected to the gate of the first MOS transistor and to the collector-emitter path of the second bipolar transistor.

19. The system of claim 18, wherein the control electrode of the first positive feedback transistor and the control electrode of the second positive feedback transistor are coupled to the mirror leg at a node connecting the source-drain path of the second MOS transistor and the collector-emitter path of the second bipolar transistor.

20. The system of claim 19, wherein the delay network comprises:

a resistor, connected on one side to the control electrode of the first positive feedback transistor, and connected on a second side to the node connecting the source-drain path of the second MOS transistor and the collector-emitter path of the second bipolar transistor; and

a capacitor, connected on one side to the control electrode of the first positive feedback transistor, and connected on a second side to a fixed voltage.