Microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface
First Claim
1. A microcontroller formed upon a single monolithic semiconductor substrate, comprising:
- a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
a plurality of I/O pads a configurable logic block (CLB) coupled to receive the plurality of CPU output signals and coupled to the plurality of I/O pads, wherein the CLB is configurable to;
(i) produce a plurality of CLB output signals in response to the plurality of CPU output signals in accordance with a programmable configuration of said CLB, and (ii) direct the CLB output signals to respective said I/O pads in accordance with a predefined hardware interface attributed to the programmable configuration; and
programming hardware coupled to the CLB for programming the CLB such that the programmable configuration of the CLB is achieved.
6 Assignments
0 Petitions
Accused Products
Abstract
A microcontroller is presented having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface. The microcontroller includes a central processing unit (CPU), a first set of I/O pads, and a configurable logic block (CLB) all formed upon a single monolithic semiconductor substrate. The CPU is configured to execute instructions, preferably x86 instructions. The CPU produces CPU output signals during instruction execution. The CLB is coupled between the CPU output signals and the first set of I/O pads, and is configurable to perform a logic function selected from a predefined set of logic functions. Each member of the set of logic functions has an associated hardware interface including a signal table which defines a correspondence between CLB input/output signals and members of the first set of I/O pads. The microcontroller also preferably includes a test/program core coupled to a second set of I/O pads and to the CLB. The test/program core produces programming signals in response to signals received via the second set of I/O pads. The programming signals cause the CLB to perform the selected logic function. When programmed, the CLB produces CLB output signals in response to the CPU output signals. Each of the CLB output signals is coupled to one or more of the members of the first set of I/O pads according to the hardware interface of the selected logic function.
75 Citations
28 Claims
-
1. A microcontroller formed upon a single monolithic semiconductor substrate, comprising:
-
a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
a plurality of I/O pads a configurable logic block (CLB) coupled to receive the plurality of CPU output signals and coupled to the plurality of I/O pads, wherein the CLB is configurable to;
(i) produce a plurality of CLB output signals in response to the plurality of CPU output signals in accordance with a programmable configuration of said CLB, and (ii) direct the CLB output signals to respective said I/O pads in accordance with a predefined hardware interface attributed to the programmable configuration; and
programming hardware coupled to the CLB for programming the CLB such that the programmable configuration of the CLB is achieved. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A microcontroller formed upon a single monolithic semiconductor substrate, comprising:
-
an internal bus having a plurality of signal lines for conveying signals;
a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
a first plurality of I/O pads;
a configurable logic block (CLB) coupled between the internal bus and the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface;
a second plurality of I/O pads; and
a test/program core coupled to the second plurality of I/O pads and to the CLB, wherein the test/program core is configured to produce programming signals in response to signals received via the second plurality of I/O pads;
wherein the CLB is configured to perform a selected logic function by the programming signals, and wherein the configured CLB produces a plurality of CLB output signals in response to the plurality of CPU output signals such that each of the plurality of CLB output signals is coupled to one or more of the first plurality of I/O pads according to the hardware interface of the selected logic function. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
a third plurality of I/O pads; and
a memory controller coupled to the internal bus and to the third plurality of I/O pads, wherein the memory controller is configured to control the saving of data within and the retrieving of data from one or more memory devices coupled to the third plurality of I/O pads.
-
-
16. The microcontroller as recited in claim 9, further comprising:
-
a third plurality of I/O pads; and
an expansion bus interface coupled to the internal bus and to the third plurality of I/O pads, wherein the expansion bus interface is configured to control an expansion bus coupled to the third plurality of I/O pads.
-
-
17. A microcontroller formed upon a single monolithic semiconductor substrate, comprising:
-
an internal bus having a plurality of signal lines for conveying signals;
a CPU coupled to the internal bus and configured to execute instructions, wherein the CPU produces a plurality of CPU output signals during instruction execution;
a first plurality of I/O pads;
a configurable logic block (CLB) coupled between the internal bus and the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface;
a second plurality of I/O pads;
a test/program core coupled to the second plurality of I/O pads and to the CLB, wherein the test/program core is configured to produce programming signals in response to signals received via the second plurality of I/O pads;
a third plurality of I/O pads;
a memory controller coupled to the internal bus and to the third plurality of I/O pads, wherein the memory controller is configured to control the saving of data within and the retrieving of data from one or more memory devices coupled to the third plurality of I/O pads;
a fourth plurality of I/O pads; and
an expansion bus interface coupled to the internal bus and to the fourth plurality of I/O pads, wherein the expansion bus interface is configured to control an expansion bus coupled to the fourth plurality of I/O pads;
wherein the CLB is configured to perform a selected logic function by the programming signals, and wherein the configured CLB produces a plurality of CLB output signals in response to the plurality of CPU output signals such that each of the plurality of CLB output signals is coupled to one or more of the first plurality of I/O pads according to the hardware interface of the selected logic function. - View Dependent Claims (18, 19, 20)
-
-
21. A microcontroller, comprising:
-
a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
a plurality of I/O pads;
a configurable logic block (CLB) coupled to receive the plurality of CPU output signals and coupled to the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface; and
programming hardware coupled to the CLB for configuring the CLB to perform the selected logic function. - View Dependent Claims (22, 23, 24)
-
-
25. A microcontroller, comprising:
-
a CPU configured to execute instructions and to produce a plurality of CPU output signals during instruction execution;
a first plurality of I/O pads;
a configurable logic block (CLB) coupled to receive the plurality of CPU output signals and coupled to the first plurality of I/O pads, wherein the CLB is configurable to perform a logic function selected from a predefined set of logic functions, and wherein each member of the predefined set of logic functions has a corresponding hardware interface;
a second plurality of I/O pads; and
programming hardware coupled to the second plurality of I/O pads and to the CLB, wherein the programming hardware is configured to produce programming signals in response to signals received via the second plurality of I/O pads, and wherein the programming signals configure the CLB to perform the selected logic function. - View Dependent Claims (26, 27, 28)
-
Specification