Method and apparatus for elimination of parasitic bipolar action in logic circuits for history removal under stack contention including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements
First Claim
1. An apparatus with reduced bipolar transistor action including a dynamic logic circuit and a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device, comprising:
- a plurality of stacked SOI MOS devices interconnected to perform a predetermined logic function defining a shared node and an intermediate node; and
a plurality of series connected active discharging devices defining a discharge path between said intermediate node and a common discharge potential, said plurality of series connected active discharging devices being controlled by respective inputs to said stacked SOI MOS devices;
wherein said plurality of series connected active discharging devices selectively discharge said intermediate node through said discharge path to said common discharge potential to eliminate parasitic bipolar transistor action in said stacked SOI MOS devices.
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Abstract
The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by eliminating the effects the sneak current discharging path by applying a contention free arrangement methodology to realize the dynamic logic circuit. The SOI MOS devices are arranged so as to eliminate the effects of electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.
73 Citations
37 Claims
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1. An apparatus with reduced bipolar transistor action including a dynamic logic circuit and a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device, comprising:
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a plurality of stacked SOI MOS devices interconnected to perform a predetermined logic function defining a shared node and an intermediate node; and
a plurality of series connected active discharging devices defining a discharge path between said intermediate node and a common discharge potential, said plurality of series connected active discharging devices being controlled by respective inputs to said stacked SOI MOS devices;
wherein said plurality of series connected active discharging devices selectively discharge said intermediate node through said discharge path to said common discharge potential to eliminate parasitic bipolar transistor action in said stacked SOI MOS devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
a first transistor having a body, a drain terminal, a source terminal, and a gate input terminal;
a second transistor having a body, a drain terminal, a source terminal, and a gate input terminal; and
said first and second transistors being operatively coupled.
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10. The apparatus according to claim 9 wherein said source terminal of said first transistor is coupled to said drain terminal of said second transistor defining a node.
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11. The apparatus according to claim 10 wherein said active discharging device is a transistor having
a drain operatively coupled to said defined node; -
a gate operatively coupled to said gate input terminal; and
a source operatively coupled to a circuit common node.
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12. The apparatus according to claim 11 wherein said transistors are N type Field Effect Transistors (NFET) and said active discharging device is a P type Field Effect Transistors (PFET).
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13. The apparatus according to claim 11 wherein said transistors are P type Field Effect Transistors (PFET) and said active precharging device is a N type Field Effect Transistors (NFET).
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14. The apparatus according to claim 11 further comprising a plurality of said stacked transistors.
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15. The apparatus according to claim 14 wherein said plurality of said stacked transistors are connected in a parallel configuration.
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16. The apparatus according to claim 15 wherein said stacked transistors are N type Field Effect Transistors (NFET) and said active discharging devices are P type Field Effect Transistors (PFET).
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17. The apparatus according to claim 15 wherein said stacked transistors are P type Field Effect Transistors (PFET) and said active precharging device are N type Field Effect Transistors (NFET).
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18. A method of providing an apparatus with reduced bipolar transistor action including a dynamic logic circuit and a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device, the method comprising:
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providing a plurality of stacked SOI MOS devices interconnected to perform a predetermined logic function defining a shared node and an intermediate node;
providing a plurality of series connected active discharging devices defining a discharge path between said intermediate node and a common discharge potential, said plurality of series connected active discharging devices being controlled by respective inputs to said stacked SOI MOS devices; and
arranging said plurality of series connected active discharging devices to selectively discharge said intermediate node to said common discharge potential to eliminate parasitic bipolar transistor action in said stacked SOI MOS devices. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33)
providing a first transistor having a body, a drain terminal, a source terminal, and a gate input terminal;
providing a second transistor having a body, a drain terminal, a source terminal, and a gate input terminal; and
operatively coupling said first and second transistors.
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26. The method according to claim 25 further comprising
coupling said source terminal of said first transistor to said drain terminal of said second transistor defining a node. -
27. The method according to claim 26 wherein said active discharging device is a transistor comprising
operatively coupling a drain of said transistor to said defined node; -
operatively coupling a gate of said transistor to said gate input terminal; and
operatively coupling a source of said transistor to a circuit common node.
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28. The method according to claim 27 wherein said transistors are N type Field Effect Transistors (NFET) and said active discharging device is a P type Field Effect Transistors (PFET).
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29. The method according to claim 27 wherein said transistors are P type Field Effect Transistors (PFET) and said active precharging device is a N type Field Effect Transistors (NFET).
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30. The method according to claim 27 further comprising providing a plurality of said stacked transistors.
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31. The method according to claim 30 wherein providing said plurality of said stacked transistors comprises connecting said stacked transitors in a parallel configuration.
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32. The method according to claim 31 wherein said stacked transistors are N type Field Effect Transistors (NFET) and said active discharging devices are P type Field Effect Transistors (PFET).
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33. The method according to claim 31 wherein said stacked transistors are P type Field Effect Transistors (PFET) and said active precharging device are N type Field Effect Transistors (NFET).
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34. A Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) circuit for implementing a logic function, comprising:
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a precharge node precharged by a precharge device;
an output device coupled to said precharge node;
a logic network, said logic network selectively discharging said precharge node to a common discharge potential in response to a plurality of inputs to implement a pre-defined logic function, said logic network comprising an intermediate node; and
an active discharge path from said intermediate node to said common discharge potential, said active discharge path selectively discharging said intermediate node to said common discharge potential to prevent parasitic bipolar transistor action. - View Dependent Claims (35, 36, 37)
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Specification