Distributed gain line driver amplifier including improved linearity

• US 6,188,284 B1
• Filed: 04/23/1999
• Issued: 02/13/2001
• Est. Priority Date: 04/23/1999
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Shulman, Dima David
• Primary Examiner(s): Lee, Benny
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/299,142
• Time in Patent Office: 662 Days
• Field of Search: 330/51, 330/124.R, 330/129, 330/136, 330/295
• US Class Current: 330/295
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2203/45676 the LC comprising one cascode current mirror
• CPC Class Codes: H03F 3/303 using opamps as driving stages
• CPC Class Codes: H03F 3/3057 with asymmetrical driving of the end stage
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel

Abstract

Improved linearity in a line driver amplifier is realized by employing one or more amplifier sections each including an adaptive gain amplifier connected in parallel with a distributed gain amplifier. In an embodiment of the invention, first and second amplifier sections are connected in circuit relationship to an input and an output of the line driver amplifier to form a symmetrical amplifier configuration. In a specific embodiment of the invention, the adaptive gain amplifiers in each amplifier section are class AB type amplifiers and the distributed gain amplifiers in each amplifier section are class B amplifiers. Specifically, each of the distributed gain class B amplifiers each include a plurality of output transistors and a corresponding plurality of auxiliary amplifiers. The output transistor and auxiliary amplifier pairs are connected in parallel. Each of the auxiliary amplifiers includes a built in voltage offset, beginning with an auxiliary amplifier having the smallest voltage offset to the auxiliary amplifier having the largest offset. The individual auxiliary amplifiers maintain their corresponding output transistors in an OFF state so long as the overall amplifier input signal has a magnitude less than the auxiliary amplifier offset voltage level. When the input signal magnitude level is equal to or greater than the offset level of an auxiliary amplifier, that auxiliary amplifier turns its corresponding output transistor to an ON state. Thus, for lower magnitude input signals fewer than all of the output transistors are in an ON state, while for maximum magnitude input signals all of the output transistors are in an ON state. Use of the auxiliary amplifier-output transistor pairs allows use of smaller size transistors, each of which has a lower output current than an equivalent single output transistor. Since all of the output transistors in each amplifier stage are connected in parallel, the amplifier output current is the sum of the currents passing through the ON output transistors. Moreover, the adaptive gain class AB amplifier'"'"'s gain varies as a function of input signal such that for larger input signals there is more gain and, consequently, less distortion. By employing the adaptive gain amplifiers and distributed gain amplifiers the line driver amplifier open loop gain characteristic is much smoother resulting in increased linearity.

Claims

1. A line driver amplifier comprising:

at least one adaptive gain amplifier; and

at least one distributed gain amplifier connected in parallel with said adaptive gain amplifier,

said at least one distributed gain amplifier includes at least a first distributed gain amplifier stage including a first plurality of auxiliary amplifiers, each of said auxiliary amplifiers in said first plurality of auxiliary amplifiers having an input and an output and including a prescribed offset voltage level, and a first plurality of output transistors, each of said output transistors in said first plurality of output transistors being in a prescribed circuit relationship with the output of a respective one of said first plurality of auxiliary amplifiers forming a first plurality of auxiliary amplifier-output transistor pairs that are connected in parallel circuit relationship with each other, wherein each of said output transistors in said first plurality of output transistors is in an OFF state until an input signal supplied to the inputs of said first plurality of auxiliary amplifiers has a signal magnitude equal to or greater than the offset voltage level of the respective auxiliary amplifier in circuit relationship to said respective output transistor, whereby abrupt changes in a transfer function of said line driver amplifier are smoothed out.

2. The invention as defined in claim 1 wherein said at least one adaptive gain amplifier includes a first adaptive gain amplifier stage and a second adaptive gain amplifier stage connected in a symmetrical configuration.

3. The invention as defined in claim 2 wherein said at least one adaptive gain amplifier is a class AB amplifier.

4. The invention as defined in claim 1 wherein said at least one adaptive gain amplifier includes a differential amplifier having current mirror load impedances and an output transistor.

5. The invention as defined in claim 4 wherein said differential amplifier has first and second inputs and when signals supplied to said first and second inputs are balanced, currents flowing through said current mirror loads are balanced, and for large input signals said differential amplifier is in a transient mode of operation and said current mirror loads cause gain of said differential amplifier to increase thereby causing a significantly larger current to flow through said output transistor than when the inputs are symmetrical, whereby linearity of said line driver amplifier is improved and distortion is decreased.

6. The invention as defined in claim 5 wherein said output transistor is a field effect transistor and said line driver amplifier is implemented in CMOS technology.

7. The invention as defined in claim 3 wherein said at least one distributed gain amplifier includes said first distributed gain amplifier stage and a second distributed gain amplifier stage connected in a symmetrical configuration.

8. The amplifier as defined in claim 7 wherein said distributed gain amplifier is a class B amplifier.

9. The invention as defined in claim 1 wherein said at least one distributed gain amplifier includes said first distributed gain amplifier stage and a second distributed gain amplifier stage connected in a symmetrical configuration.

10. The amplifier as defined in claim 9 wherein said at least one distributed gain amplifier is a class B amplifier.

11. The invention as defined in claim 1 wherein said offset voltages of said first plurality of auxiliary amplifiers are set at values so that additional ones of said first plurality of output transistors are driven into an ON state with increased magnitude of said input signal.

12. The invention as defined in claim 11 wherein when said input signal has a magnitude less than a prescribed minimum value all of said first plurality of output transistors are in an OFF state and when said input signal has a magnitude greater than a prescribed maximum value all of said first plurality of output transistors are in an ON state.

13. The invention as defined in claim 12 wherein each of said first plurality of output transistors is smaller in size and carries less current when in an ON state than that of an equivalent single output transistor, if said equivalent single transistor were to be used in place of said first plurality of output transistors.

14. The invention as defined in claim 13 wherein said transistors are field effect transistors and said line driver amplifier is implemented in CMOS technology.

15. The invention as defined in claim 11 wherein each of said first plurality of auxiliary amplifiers has a prescribed internally generated offset voltage.

16. The invention as defined in claim 15 wherein said offset voltage of each of said first plurality of auxiliary amplifiers is controllably selectable.

17. The invention as defined in claim 15 wherein said offset voltage of each of said first plurality of auxiliary amplifiers has a voltage value different than said offset voltages for others of said first plurality of auxiliary amplifiers.

18. The invention as defined in claim 17 wherein each of said first plurality of auxiliary amplifiers includes at least one differential pair of first and second transistors and said offset voltage is generated by causing a current mismatch flowing through said first transistor relative to said second transistor.

19. The invention as defined in claim 18 wherein said current mismatch is obtained by the size of said first transistor being different from the size of said second transistor.

20. The invention as defined in claim 1 wherein said at least one distributed gain amplifier further includes a second distributed gain amplifier stage, said second distributed distributed gain amplifier stage being connected in circuit with said first distributed distributed gain amplifier stage wherein said at least one distributed gain amplifier is arranged as a symmetrical at least one distributed gain amplifier.

21. The invention as defined in claim 20 wherein said second distributed gain amplifier stage includes a second plurality of auxiliary amplifiers, each of said auxiliary amplifiers in said second plurality of auxiliary amplifiers having an input and an output and including a prescribed offset voltage level, and a second plurality of output transistors, each of said output transistors in said second plurality of output transistors being in a prescribed circuit relationship with the output of a respective one of said second plurality of auxiliary amplifiers forming a second plurality of auxiliary amplifier-output transistor pairs that are connected in parallel circuit relationship with each other, wherein each of said output transistors in said second plurality of output transistors is in an OFF state until an input signal supplied to the inputs of said second plurality of auxiliary amplifiers has a signal magnitude equal to or greater than the offset voltage level of the respective auxiliary amplifier in circuit relationship to said respective output transistor, whereby linearity in the frequency domain of said amplifier is improved.

22. The invention as defined in claim 21 wherein said offset voltages of said first and second plurality of auxiliary amplifiers are set at values so that additional ones of said first and second pluralities of output transistors are driven into an ON state with increased magnitude of said input signal.

23. The invention as defined in claim 22 wherein when said input signal has a magnitude less than a prescribed minimum value all of said first and second pluralities of output transistors are in an OFF state and when said input signal has a magnitude greater than a prescribed maximum value all of said first and second plurality of output transistors are in an ON state.

24. The invention as defined in claim 23 wherein each of said first and second pluralities of output transistors is smaller in size and carries less current when in an ON state than that of an equivalent single output transistor, if a first equivalent single transistor were to be used in place of said first plurality of output transistors and if a second equivalent single transistor were to be used in place of said second plurality of output transistors.

25. The invention as defined in claim 24 wherein said transistors are field effect transistors and said line driver amplifier is implemented in CMOS technology.

26. The invention as defined in claim 21 wherein each auxiliary amplifier of said first and second pluralities of auxiliary amplifiers has a prescribed internally generated offset voltage.

27. The invention as defined in claim 26 wherein said offset voltage of each of said first plurality of auxiliary amplifiers is controllably selectable.

28. The invention as defined in claim 26 wherein said offset voltage of each of said auxiliary amplifiers of said first and second pluralities of auxiliary amplifiers has a voltage value different than said offset voltages for others of said first plurality of auxiliary amplifiers and said second plurality of auxiliary amplifiers, respectively.

29. The invention as defined in claim 26 wherein each auxiliary amplifier of said first plurality and second pluralities of auxiliary amplifiers includes at least one differential pair of first and second transistors and said offset voltage is generated by causing a current mismatch flowing through said first transistor relative to said second transistor.

30. The invention as defined in claim 29 wherein said current mismatch is obtained by the size of said first transistor being different from the size of said second transistor.

31. A line driver amplifier comprising:

an adaptive gain amplifier including a first adaptive gain amplifier stage having a first adaptive gain stage and a first associated output transistor and a second adaptive gain amplifier stage having a second adaptive gain stage and a second associated output transistor; and

a distributed gain amplifier including a first distributed gain amplifier stage having a first distributed gain stage and a first associated distributed output transistor and a second distributed gain amplifier stage having a second distributed gain stage and a second associated distributed output transistor,

said first adaptive gain amplifier stage being connected in parallel with said first distributed gain amplifier stage, and said second adaptive gain amplifier stage being connected in parallel with said second distributed gain amplifier stage,

each of said first and second distributed amplifier stages including a first and a second plurality of auxiliary amplifiers, respectively, each of said auxiliary amplifiers having an input and an output and including a prescribed offset voltage level, and each of said first and second distributed output transistors being in a prescribed circuit relationship with the output of a respective one of said first and second plurality of auxiliary amplifiers forming first and second pluralities of auxiliary amplifier-output transistor pairs that are connected in parallel circuit relationship with each other, wherein each of said distributed output transistors is in an OFF state until an input signal supplied to the inputs of said auxiliary amplifiers has a signal magnitude equal to or greater than the offset voltage level of the respective auxiliary amplifier in circuit relationship to said respective one of said distributed output transistors, whereby linearity of said line driver amplifier is improved and distortion is decreased.

32. The invention as defined in claim 31 wherein said first and second adaptive gain amplifier stages and said first and second distributed gain amplifier stages are connected such that said line driver amplifier is in a symmetrical amplifier configuration.

33. The invention as defined in claim 31 wherein adaptive gain amplifier is a class AB amplifier.

34. The invention as defined in claim 31 wherein each of said first and second adaptive gain stages includes a differential amplifier having current mirror load impedances and an output transistor.

35. The invention as defined in claim 34 wherein said differential amplifier has first and second inputs and when signals to said first and second inputs are balanced currents flowing through said current mirror loads are balanced and for large input signals said differential amplifier is in a transient mode of operation and said current mirror loads cause gain of said differential amplifier to increase thereby causing a significantly larger current to flow through said output transistor than when the inputs are balanced, whereby linearity of said line driver amplifier is improved and distortion is decreased.

36. The amplifier as defined in claim 35 wherein each of said first and second dustributed gain stages includes a class B amplifier.

37. The invention as defined in claim 31 wherein said offset voltages of said first and second plurality of auxiliary amplifiers are set at values so that additional ones of said first and second distributed output transistors are driven into an ON state with increased magnitude of said input signal.

38. The invention as defined in claim 37 wherein when said input signal has a magnitude less than a prescribed minimum value all of said first and second distributed output transistors are in an OFF state and when said input signal has a magnitude greater than a prescribed maximum value all of said first and second distributed output transistors are in an ON state.

39. The invention as defined in claim 38 wherein each of said first and second distributed output transistors is smaller in size and carries less current when in an ON state than that of an equivalent single output transistor, if a first equivalent single transistor were to be used in place of said first distributed output transistors and if a second equivalent single transistor were to be used in place of said second distributed output transistors.

40. The invention as defined in claim 31 wherein each auxiliary amplifier of said first and second pluralities of auxiliary amplifiers has a prescribed internally generated offset voltage.

41. The invention as defined in claim 40 wherein said offset voltage of each of said first plurality of auxiliary amplifiers is controllably selectable.

42. The invention as defined in claim 40 wherein said offset voltage of each of said auxiliary amplifiers of said first and second pluralities of auxiliary amplifiers has a voltage value different than said offset voltages for others of said first plurality of auxiliary amplifiers and said second plurality of auxiliary amplifiers, respectively.

43. The invention as defined in claim 41 wherein each auxiliary amplifier of said first plurality and second pluralities of auxiliary amplifiers includes at least one differential pair of first and second transistors and said offset voltage is generated by causing a current mismatch flowing through said first transistor relative to said second transistor.

44. The invention as defined in claim 43 wherein said current mismatch is obtained by the size of said first transistor being different from the size of said second transistor.