Differential multiplexer and differential logic circuit

• US 6,188,339 B1
• Filed: 01/13/1999
• Issued: 02/13/2001
• Est. Priority Date: 01/23/1998
• Status: Expired due to Fees

• Current Assignee: Fujifilm Corporation (Fujifilm Holdings Corporation)
• Original Assignee: Fuji Photo Film Co Limited (Fujifilm Holdings Corporation)
• Inventors: Hasegawa, Yasumasa
• Primary Examiner(s): Young, Brian
• Assistant Examiner(s): NGUYEN, JOHN B
• Application Number:
  US09/229,673
• Time in Patent Office: 762 Days
• Field of Search: 341/101, 341/100, 326/115, 326/110, 326/112, 326/105, 327/408, 327/404, 327/416
• US Class Current: 341/101
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H03M 9/00 Parallel/series conversion or vice versa digital stores in which the information is moved stepwise per se G11C19/00

Abstract

A differential multiplexer has first and second differential input pairs for receiving first and second input signals, a transistor for making active the first differential input pair by using as a control signal a first clock of a pair of differential first and second clocks, another transistor for making active the second differential input pair by using as a control signal the second clock, a first output terminal for outputting the first input signal if the first clock is larger than the second clock and outputting the second input signal if the second clock is larger than the first clock, and a second output terminal for outputting a paired differential signal of the signal output from the first output terminal.

Claims

1. A differential multiplexer comprising:

a first differential input pair including first and second transistors, the first differential input pair using as control signals a first input signal and an inverted first input signal;

a second differential input pair including third and fourth transistors, the second differential input pair using as control signals a second input signal and an inverted second input signal;

a fifth transistor for making active the first differential input pair by using as a control signal a first clock of first and second clocks forming a pair of differential clocks;

a sixth transistor for making active the second differential input pair by using as a control signal the second clock;

a first constant current source for supplying a constant current to branched paths to the first and third transistors;

a second constant current source for supplying a constant current to branched paths to the second and fourth transistors, the first and second current sources constituting a current mirror;

a first output terminal connected to the branch paths of the second and fourth transistors for outputting the first input signal when the first clock is larger than the second clock, and outputting the second input signal when the second clock is larger than the first clock; and

a second output terminal connected to the first and third transistors for outputting a paired differential signal of a signal output from the first output terminal.

2. A differential multiplexer according to claim 1, wherein the first to sixth transistors are MOS transistors.

3. A differential multiplexer according to claim 2, wherein the first and second constant current sources are made of MOS transistors.

4. A differential multiplexer according to claim 1, wherein:

the first to sixth transistors are n-channel MOS transistors each having a gate, a source, and a drain;

the first input signal is applied to the gate of the first transistor, the inverted first input signal is applied to the gate of the second transistor, the second input signal is applied to the gate of the third transistor, the inverted second input signal is applied to the gate of the fourth transistor;

the first clock is applied to the gate of the fifth transistor, and the second clock is applied to the gate of the sixth transistor;

the drain of the fifth transistor is connected to the sources of the first and second transistors, and the source thereof is connected to a ground terminal;

the drain of the sixth transistor is connected to the sources of the third and fourth transistors, and the source thereof is connected to the ground terminal; and

the drains of the first and third transistors are connected to the first current source, and the drains of the second and fourth transistors are connected to the second current source.

5. A differential multiplexer according to claim 1, further comprising an output stage connected to the first and second output terminals for current-amplifying the signal output from the first and second output terminals.

8. A differential multiplexer according to claim 1, further comprising:

a first inverter for generating the inverted first input signal and outputting the inverted first input signal to the first differential input pair; and

a second inverter for generating the inverted second input signal and outputting the inverted second input signal to the second differential input pair.

21. A differential multiplexer according to claim 4, wherein the source of the fifth transistor and the source of the sixth transistor are each directly connected to ground.

6. A differential multiplexer comprising

a first differential input pair including first and second transistors, the first differential input pair using as control signals a first input signal and an inverted first input signal;

a second differential input pair including third and fourth transistors, the second differential input pair using as control signals a second input signal and an inverted second input signal;

a fifth transistor for making active the first differential input pair by using as a control signal a first clock of first and second clocks forming a pair of differential clocks;

a sixth transistor for making active the second differential input pair by using as a control signal the second clock;

a first constant current source for supplying a constant current to branched paths to the first and third transistors;

a second constant current source for supplying a constant current to branched paths to the second and fourth transistors, the first and second current sources constituting a current mirror;

a first output terminal connected to the branch paths of the second and fourth transistors for outputting the first input signal when the first clock is larger than the second clock, and outputting the second input signal when the second clock is larger than the first clock;

a second output terminal connected to the first and third transistors for outputting a paired differential signal of a signal output from the first output terminal;

wherein the first to sixth transistors are n-channel MOS transistors each having a gate, a source, and a drain and the first input signal is applied to the gate of the first transistor, the inverted first input signal is applied to the gate of the second transistor, the second input signal is applied to the gate of the third transistor, the inverted second input signal is applied to the gate of the fourth transistor, the first clock is applied to the gate of the fifth transistor, and the second clock is applied to the gate of the sixth transistor, the drain of the fifth transistor is connected to the sources of the first and second transistors, and the source thereof is connected to a ground terminal, the drain of the sixth transistor is connected to the sources of the third and fourth transistors, and the source thereof is connected to the ground terminal, and the drains of the first and third transistors are connected to the first current source, and the drains of the second and fourth transistors are connected to the second current source; and

a positive potential power source terminal;

wherein the first and second current sources are seventh and eighth p-channel MOS transistors, respectively, each having a gate, a source, and a drain, the gate of the seventh p-channel MOS transistor is connected to the gate of the eighth p-channel MOS transistor, the drain of the seventh p-channel MOS transistor is connected to the drains of the first and third transistors, the source of the seventh p-channel MOS transistor is connected to the positive potential power source terminal, and the drain of the eighth p-channel MOS transistor is connected to the drains of the second and fourth transistors, and the source of the eighth p-channel MOS transistor is connected to the positive potential power source terminal.

7. A differential multiplexer according to claim 6, further comprising:

a ninth p-channel MOS transistor whose gate and drain are connected in common to the gate of the seventh and eighth p-channel MOS transistors and whose source is connected to the positive potential power source terminal; and

a third current source whose one end is connected to the ground terminal and whose another end is connected to the drain of the ninth p-channel MOS transistor.

17. A differential multiplexer according to claim 6, wherein the first to sixth transistors are MOS transistors.

18. A differential multiplexer according to claim 17, wherein the first and second constant current sources are made of MOS transistors.

19. A differential multiplexer according to claim 6, further comprising an output stage connected to the first and second output terminals for current-amplifying the signal output and the first and second output terminals.

20. A differential multiplexer according to claim 6, further comprising a first inverter for generating the inverted first input signal and outputting the inverted first input signal to the first differential input pair, and a second inverter for generating the inverted second input signal and outputting the inverted second input signal to the second differential input pair.

9. A parallel-serial conversion differential logic circuit comprising:

parallel-serial converting means for converting a parallel signal into a serial signal, the parallel-serial converting means including a plurality of selectors and a plurality of double-edge trigger flip-flops using a first clock as a trigger, the selectors and flip-flops being respectively connected in series;

first serial-parallel converting means for converting the serial signal converted by the parallel-serial converting means into two-bit parallel signals, the first serial-parallel converting means including two single edge trigger flip-flops using a second clock as a trigger, the second clock having a same frequency as the first clock; and

a first differential multiplexer for selecting one bit signal of the two-bit parallel signals converted by the first serial-parallel converting means, in accordance with which one of a pair of differential clocks having opposite phases and a same frequency as the first clock is larger, and serially outputting the one bit signal at a speed corresponding to a speed of a clock having a twofold frequency of the first clock.

10. A parallel-serial conversion differential logic circuit according to claim 9, wherein the first differential multiplexer selects one bit signal of the two-bit parallel signals converted by the first serial-parallel converting means and serially outputs a pair of differential signals of the one bit signal having opposite phases at a speed corresponding to a speed of a clock having a twofold frequency of the first clock.

11. A parallel-serial conversion differential logic circuit according to claim 9, further comprising clock generating means for generating the pair of differential clocks and generating the first and second clocks from the pair of generated differential clocks.

12. A parallel-serial conversion differential logic circuit according to claim 9, wherein the first and second clocks are a same clock.

13. A parallel-serial conversion differential logic circuit according to claim 9, further comprising:

an exclusive logical sum circuit for calculating a logical sum of a third clock having a same frequency as the first clock and the serial signal converted by the parallel-serial converting means and outputting the serial signal in accordance with the calculated logical sum;

second serial-parallel converting means for converting the serial signal output from the exclusive logical sum circuit into two-bit parallel signals, the second serial-parallel converting means including two single edge flip-flops using the second clock as a trigger; and

a second differential multiplexer for selecting one bit signal of the two-bit parallel signals converted by the second serial-parallel converting means, in accordance with which one of the pair of differential clocks is larger, and serially outputting the one bit signal at a speed corresponding to a speed of a clock having a twofold frequency of the first clock.

14. A parallel-serial conversion differential logic circuit according to claim 13, wherein the first and second differential multiplexers each output a pair of differential signals of the selected one bit signal having opposite phases.

15. A parallel-serial conversion differential logic circuit according to claim 10, wherein the first differential multiplexer comprises:

a first differential input pair including first and second transistors, the first differential input pair using as control signals a first input signal and an inverted first input signal;

a second differential input pair including third and fourth transistors, the second differential input pair using as control signals a second input signal and an inverted second input signal;

a fifth transistor for making active the first differential input pair by using as a control signal a first clock of first and second clocks forming a pair of differential clocks;

a sixth transistor for making active the second differential input pair by using as a control signal the second clock;

a first constant current source for supplying a constant current to branched paths to the first and third transistors;

a second constant current source for supplying a constant current to branched paths to the second and fourth transistors, the first and second current sources constituting a current mirror;

a first output terminal connected to the branch paths of the second and fourth transistors for outputting the first input signal when the first clock is larger than the second clock, and outputting the second input signal when the second clock is larger than the first clock; and

a second output terminal connected to the first and third transistors for outputting a paired differential signal of a signal output from the first output terminal.

16. A parallel-serial conversion differential logic circuit according to claim 14, wherein the first and second differential multiplexers each comprises:

a first differential input pair including first and second transistors, the first differential input pair using as control signals a first input signal and an inverted first input signal;

a second differential input pair including third and fourth transistors, the second differential input pair using as control signals a second input signal and an inverted second input signal;

a fifth transistor for making active the first differential input pair by using as a control signal a first clock of first and second clocks forming a pair of differential clocks;

a sixth transistor for making active the second differential input pair by using as a control signal the second clock;

a first constant current source for supplying a constant current to branched paths to the first and second transistors;

a second constant current source for supplying a constant current to branched paths to the second and fourth transistors, the first and second current sources constituting a current mirror;

a first output terminal connected to the branch paths of the second and fourth transistors for outputting the first input signal when the first clock is larger than the second clock, and outputting the second input signal when the second clock is larger than the first clock; and

a second output terminal connected to the first and third transistors for outputting a paired differential signal of a signal output from the first output terminal.