Internal row sequencer for reducing bandwidth and peak current requirements in a display driver circuit

• US 6,188,377 B1
• Filed: 03/25/1998
• Issued: 02/13/2001
• Est. Priority Date: 11/14/1997
• Status: Expired due to Term

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Aurora Systems Inc (Allegion PLC)
• Inventors: Hudson, Edwin Lyle, Campbell, John Gray
• Primary Examiner(s): Liang, Regina
• Application Number:
  US09/047,947
• Time in Patent Office: 1,056 Days
• Field of Search: 345/98, 345/100, 345/94, 345/87, 345/84, 345/204, 348/714-719
• US Class Current: 345/98
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 2310/02 Addressing, scanning or driving the display screen or processing steps related thereto
• CPC Class Codes: G09G 2310/0221 with use of split matrices G09G3/3644 and G09G3/3666 take precedence
• CPC Class Codes: G09G 2310/0254 Control of polarity reversal in general, other than for liquid crystal displays
• CPC Class Codes: G09G 2310/0262 The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2330/025 Reduction of instantaneous peaks of current
• CPC Class Codes: G09G 2370/08 Details of image data interface between the display device controller and the data line driver circuit
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2085 Special arrangements for addressing the individual elements of the matrix, other than by driving respective rows and columns in combination
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A display driver circuit includes a word line sequencer for providing a series of row addresses, and a row decoder for decoding each of the row addresses and asserting write signals on corresponding ones of a plurality of output terminals. An optional data path sequencer provides a series of path addresses which are used by an optional data router to route data to particular sub-rows of a display. Additionally, an optional sub-row sequencer provides a series of sub-row addresses to an optional sub-row decoder, which decodes each of the sub-row addresses and asserts write signals on corresponding ones of a second plurality of output terminals. In various embodiments, the row sequencer, the sub-row sequencer, and/or the data path sequencer is/are responsive to data load instructions from a system, such that no Array Write commands are required to write data to a display.

Claims

1. A display driver circuit for receiving data and data load instructions from a system, and for driving a display having a plurality of data input lines and a first plurality of word lines, each word line being associated with a portion of said display, such that write signals asserted on said word lines cause data asserted on said data input lines to be loaded into said associated portions of said display, said display driver circuit comprising:

data processing means responsive to said data load instructions and operative upon receipt of each said data load instruction to receive a first predetermined quantity of data from said system, to accumulate said data, and to assert the accumulated data on said data input lines of said display when a second predetermined quantity of data is accumulated; and

display portion selecting means for receiving said data load instructions and for generating write signals for causing data to be loaded into said associated portions of said display, said display portion selecting means being operative to assert a first write signal on a first one of said word lines causing data initially asserted on said data input lines to be loaded into an associated portion of said display, and to determine from said data load instructions when a third predetermined quantity of data has been subsequently asserted on said data input lines, and in response thereto, asserting a second write signal onto a second word line associated with a second portion of said display, said display portion selecting means thereafter continuing to determine each time a third predetermined quantity of data has been subsequently asserted on said data input lines, and in response thereto, asserting a subsequent write signal onto a subsequent word line associated with a subsequent portion of said display, until all incoming data has been received.

2. A display driver circuit according to claim 1, wherein said display portion selecting means comprises:

a row sequencer responsive to said data load instructions and operative to provide a series of row addresses, said row sequencer providing each subsequent row address responsive to receipt of a first predetermined number of said data load instructions; and

a row decoder responsive to said series of row address and operative to assert a write signal on one of said first plurality of word lines corresponding to each of said row addresses.

3. A display driver circuit according to claim 2, wherein said display portion selecting means Further comprises a row address register, operative to provide an initial row address to said row sequencer.

4. A display driver circuit according to claim 3, wherein said row address register, responsive to a load row address instruction from said system, is further operative to receive another initial row address from said system and to provide said another initial row address to said row sequencer.

5. A display driver circuit according to claim 4, wherein said row sequencer, responsive to said load row address instruction and said another initial row address, is operative to provide a new series of row addresses starting from said another initial row address.

6. A display driver circuit according to claim 2, wherein said display further includes a second plurality of word lines, each of which is associated with a portion of said display, such that the simultaneous assertion of write signals on one of said first plurality of word lines and on one of said second plurality of word lines causes data asserted on said data input lines to be loaded into a particular portion of said display, and wherein said display portion selecting means further comprises:

a sub-row sequencer responsive to said data load instructions and operative to provide a series of sub-row addresses, said sub-row sequencer providing each subsequent sub-row address responsive to receipt of a second predetermined number of said data load instructions; and

a sub-row decoder responsive to said series of sub-row addresses and operative to assert a write signal on one of said second plurality of word lines corresponding to each of said sub-row addresses.

7. A display driver circuit according to claim 1, wherein said display portion selecting means comprises:

a sub-row sequencer responsive to said data load instructions and operative to provide a series of sub-row addresses, said sub-row sequencer providing each subsequent sub-row address responsive to receipt of a predetermined number of said data load instructions; and

a sub-row decoder responsive to said series of sub-row address and operative to assert a write signal on one of said first plurality of word lines corresponding to each of said sub-row addresses.

8. A display driver circuit according to claim 1, wherein said data processing means asserts the accumulated data on said data input lines responsive to receipt of a first predetermined number of said data load instructions.

9. A display driver circuit according to claim 8, wherein said data processing means comprises:

a pointer responsive to said data load instructions and operative to provide a series of register portion addresses, said pointer providing each subsequent register portion address responsive to receipt of one of said data load instructions;

a data path sequencer responsive to said data load instructions and operative to provide a series of path addresses, said data path sequencer providing each subsequent path address responsive to receipt of said first predetermined number of said data load instructions;

a register responsive to said series of register portion addresses and said data load instructions and operative to receive said data from said system and store said data in portions of said register corresponding to said register portion addresses, said register being further responsive to said data path addresses and operative to provide accumulated data from groups of said register portions corresponding to said data path addresses.

10. A display driver circuit according to claim 9, further comprising a data router responsive to said series of data path addresses and operative to receive said accumulated data from said groups of said register portions and assert said accumulated data on groups of said data lines corresponding to said data path addresses.

11. A display driver circuit according to claim 9, wherein said data path sequencer comprises a counter for counting said data load instructions.

12. A display driver circuit according to claim 11, wherein said counter comprises a divide-by-n counter.

13. A display driver circuit according to claim 8, wherein said data processing means comprises:

a pointer responsive to said data load instructions and operative to provide a series of register portion addresses, said pointer providing each subsequent register portion address responsive to receipt of one of said data load instructions;

a data path sequencer responsive to said series of register portion addresses and operative to provide a series of path addresses, said data path sequencer providing each subsequent path address responsive to receipt of a first predetermined number of said register portion addresses;

a register responsive to said series of register portion addresses and said data load instructions and operative to receive said data from said system and store said data in portions of said register corresponding to said register portion addresses, said register being further responsive to said data path addresses and operative to provide accumulated data from groups of said register portions corresponding to said data path addresses.

14. A display driver circuit according to claim 13, wherein said data path sequencer comprises a counter for counting said register portion addresses.

15. A display driver circuit according to claim 14, wherein said counter comprises a divide-by-n counter.

16. A display driver circuit according to claim 13, wherein said data path sequencer comprises a decoder, for decoding said register portion addresses to generate said data path addresses.

17. A display driver circuit according to claim 13, wherein said display portion selecting means comprises:

a row sequencer responsive to said series of register portion addresses and operative to provide a series of row addresses, said row sequencer providing each subsequent row address responsive to receipt of a second predetermined number of said register portion addresses; and

a row decoder responsive to said series of row address and operative to assert a write signal on one of said first plurality of word lines corresponding to each of said row addresses.

18. A display driver circuit according to claim 1, wherein after asserting a write signal on a last one of said word lines and responsive to determining that said third predetermined quantity of data has been subsequently asserted on said data input lines, said display portion selecting means asserts another write signal on said first one of said word lines.

19. A display driver circuit according to claim 18, wherein said first one of said word lines corresponds to a top portion of said display and said last one of said word lines corresponds to a bottom portion of said display.

20. In a display driver circuit for receiving data words and data load instructions from a system, and for driving a display having a plurality of data input lines and a first plurality of word lines, each word line being associated with a portion of said display such that write signals asserted on said word lines cause data asserted on said data input lines to be loaded into said associated portions of said display, a method for driving said display comprising the steps of:

asserting a first write signal on one of said word lines;

receiving data load instructions from said system;

receiving a first predetermined quantity of data from said system responsive to each said data load instruction;

accumulating said data;

asserting the accumulated data on said data input lines each time a second predetermined quantity of data is accumulated;

determining from said data load instructions when a third predetermined quantity of data has been subsequently asserted on said data input lines; and

asserting a subsequent write signal on a subsequent word line associated with a subsequent portion of said display, each time said third predetermined quantity of data has been subsequently asserted on said data input lines.

21. A method for driving a display according to claim 20, wherein said step of asserting a subsequent write signal on a subsequent word line associated with a subsequent portion of said display, each time said third predetermined quantity of data has been subsequently asserted on said data input lines comprises the steps of:

generating a series of row addresses, each row address being generated responsive to receipt of a first predetermined number of said data load instructions;

decoding each row address; and

asserting a write signal on one of said first plurality of word lines corresponding to each decoded row address.

22. A method for driving a display according to claim 21, wherein said step of generating a series of row addresses comprises the steps of:

receiving a first initial row address; and

generating a series of row addresses based on said first initial row address.

23. A method according to claim 22, wherein said step of generating a series of row addresses further comprises the steps of:

receiving another initial row address; and

generating another series of row addresses based on said another initial row address.

24. A method according to claim 21, wherein said display further includes a second plurality of word lines, each of which is associated with a portion of said display, such that the simultaneous assertion of write signals on one of said first plurality of word lines and on one of said second plurality of word lines causes data asserted on said data input lines to be loaded into a particular portion of said display, said method further comprising the steps of:

generating a series of sub-row addresses, each sub-row address being generated responsive to receipt of a second predetermined number of said data load instructions;

decoding each sub-row address; and

asserting a write signal on one of said second plurality of word lines corresponding to each decoded sub-row address.

25. A method according to claim 20, wherein said step of asserting a subsequent write signal on a subsequent word line associated with a subsequent portion of said display, each time said third predetermined quantity of data has been subsequently asserted on said data input lines comprises the steps of:

generating a series of sub-row addresses, each sub-row address being generated responsive to receipt of a predetermined number of said data load instructions;

decoding each sub-row address; and

asserting a write signal on one of said first plurality of word lines corresponding to each decoded sub-row address.

26. A method according to claim 20, wherein said step of asserting the accumulated data on said data input lines each time a second predetermined quantity of data is accumulated comprises the steps of:

determining when a predetermined number of data load instructions have been received; and

asserting the accumulated data on said data input lines each time said predetermined number of data load instructions are received.

27. A method according to claim 26, wherein said step of accumulating said data comprises the steps of:

generating a series of register portion addresses, each subsequent register portion address being generated in response to receipt of one of said data load instructions; and

storing each first predetermined quantity of data in a portion of a register corresponding to one of said register portion addresses.

28. A method according to claim 27, wherein said step of asserting the accumulated data on said data input lines each time a second predetermined quantity of data is accumulated comprises the steps of:

generating a series of data path addresses, each subsequent data path address being generated in response to receipt of a first predetermined number of said data load instructions; and

providing the accumulated data from groups of said register portions corresponding to said data path addresses.

29. A method according to claim 27, wherein said step of asserting the accumulated data on said data input lines each time a second predetermined quantity of data is accumulated further comprises the step of asserting said accumulated data on groups of said data lines corresponding to said data path addresses.

30. A method according to claim 27, wherein said step of asserting the accumulated data on said data input lines each time a second predetermined quantity of data is accumulated comprises the steps of:

generating a series of data path addresses, each subsequent data path address being generated in response to receipt of a first predetermined number of said register portion addresses; and

providing the accumulated data from groups of said register portions corresponding to said data path addresses.

31. A method for driving a display according to claim 30, wherein said step of asserting a subsequent write signal on a subsequent word line associated with a subsequent portion of said display, each time said third predetermined quantity of data has been subsequently asserted on said data input lines comprises the steps of:

generating a series of row addresses, each row address being generated responsive to receipt of a second predetermined number of said register portion addresses;

decoding each row address; and

asserting a write signal on one of said first plurality of word lines corresponding to each decoded row address.