Mechanism to commit data to a memory device with read-only access

• US 6,188,602 B1
• Filed: 01/25/2000
• Issued: 02/13/2001
• Est. Priority Date: 01/25/2000
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Martin, Todd, Alexander, Marc D.
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): PHUNG, ANH K
• Application Number:
  US09/491,167
• Time in Patent Office: 385 Days
• Field of Search: 365/185.04, 365/185.33, 365/185.08, 365/185.22, 365/185.23
• US Class Current: 365/185.04
• CPC Class Codes: G06F 12/1466 Key-lock mechanism
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells

Abstract

An apparatus for accessing locked-down flash memory in a computer system that utilizes a general purpose input/output port coupled to the flash memory, and includes program instructions that generate a reset signal, output the reset signal to the general purpose input/output port, sense the reset signal, unlock the flash memory to allow write access to the flash memory, update the flash memory, and lock the flash memory to locked down mode. The present invention allows flash memory to be updated during normal operation of the computer system.

Claims

1. A method of updating flash memory in a computer system during operation of the computer system wherein the flash memory is in locked-down mode, the method comprising:

generating a reset signal;

outputting the reset signal on a general purpose input/output port, wherein the general purpose input/output port is coupled to reset circuitry for the flash memory;

sensing the reset signal;

unlocking the flash memory to allow write access to the flash memory;

updating the flash memory; and

locking the flash memory to locked down mode.

2. The method of claim 1 wherein the computer system is operating while the method is performed.

3. The method of claim 1 further comprising:

coupling the general purpose input/output port to existing flash memory reset circuitry.

4. The method of claim 1 wherein updating the flash memory includes updating flash memory program instructions.

5. The method of claim 1 wherein updating the flash memory includes updating BIOS program instructions.

6. The method of claim 1 further including generating the reset signal when the operating system requests access to the flash memory.

7. The method of claim 1 further including generating the reset signal when a system management interrupt requests access to the flash memory.

8. The method of claim 1 further including preventing generation of the reset signal when unauthorized access to the flash memory is requested.

9. A computer system comprising:

a processor;

a flash memory coupled to the processor;

a general purpose input/output port coupled to the flash memory;

first program instructions operable to;

generate a reset signal;

output the reset signal to the general purpose input/output port, wherein the general purpose input/output port is coupled to reset circuitry for the flash memory;

sense the reset signal;

unlock the flash memory to allow write access to the flash memory;

update the flash memory; and

lock the flash memory to locked down mode.

10. The computer system of claim 9 wherein the computer system is operating while the first program instructions are executed.

11. The computer system of claim 9 wherein the general purpose input/output port is coupled to existing flash memory reset circuitry.

12. The computer system of claim 9 wherein the program instructions update the flash memory program instructions.

13. The computer system of claim 9 wherein the program instructions update the BIOS program instructions.

14. The computer system of claim 9 wherein the program instructions generate the reset signal when the operating system requests access to the flash memory.

15. The computer system of claim 9 wherein the program instructions generate the reset signal when a system management interrupt requests access to the flash memory.

16. The computer system of claim 9 wherein the program instructions prevent generation of the reset signal when unauthorized access to the flash memory is requested.

17. An apparatus for accessing flash memory in a computer system, the apparatus comprising:

a general purpose input/output port coupled to the flash memory;

first program instructions operable to;

generate a reset signal;

output the reset signal to the general purpose input/output port, wherein the general purpose input/output port is coupled to reset circuitry for the flash memory;

sense the reset signal;

unlock the flash memory to allow write access to the flash memory;

update the flash memory; and

lock the flash memory to locked down mode.

18. The apparatus of claim 17 wherein the computer system is operating while the first program instructions are executed.

19. The apparatus of claim 17 wherein the general purpose input/output port is coupled to existing flash memory reset circuitry.

20. The apparatus of claim 17 wherein the program instructions update the flash memory program instructions.

21. The apparatus of claim 17 wherein the program instructions update the BIOS program instructions.

22. The apparatus of claim 17 wherein the program instructions generate the reset signal when the operating system requests access to the flash memory.

23. The apparatus of claim 17 wherein the program instructions generate the reset signal when a system management interrupt requests access to the flash memory.

24. The apparatus of claim 17 wherein the program instructions prevent generation of the reset signal when unauthorized access to the flash memory is requested.