Memory device with address translation for skipping failed memory blocks

• US 6,188,619 B1
• Filed: 06/24/1999
• Issued: 02/13/2001
• Est. Priority Date: 10/09/1998
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Seong-ook
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/339,377
• Time in Patent Office: 600 Days
• Field of Search: 365/200, 365/230.03, 365/230.02, 365/230.06, 365/225.7
• US Class Current: 365/200
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 29/883 using a single defective memory device with reduced capacity, e.g. half capacity
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A semiconductor memory device capable of operating normally even when a failed memory cell remains after repair. The semiconductor memory device includes a plurality of memory cell array blocks, and address decoding circuitry for receiving an address and for accessing good memory cell array blocks and skipping failed memory cell array blocks.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cell array blocks, wherein each memory cell array block comprises a plurality of memory cells, each memory cell being either good or defective;

address decoding circuitry for receiving an address;

a selection signal generator for generating a selection signal indicating which blocks have good memory cells and which blocks have at least one bad memory cell; and

a multiplexer responsive to the address decoding circuitry and the selection signal for generating an internal address for accessing memory cell array blocks having good memory cells and skipping memory cell array blocks having at least one defective memory cell.

2. The semiconductor memory device of claim 1, wherein the address decoding circuitry comprises a plurality of fuses for designating which memory cell array blocks have only good memory cells and which memory cell array blocks have at least one defective memory cell, the fuses being adapted to be cut, and wherein the at least one selection signal is generated according to which fuses are cut.

3. The semiconductor memory device of claim 1, further comprising:

a buffer for buffering the internal address of the multiplexer for accessing the memory cell array blocks and for enabling only the internal address corresponding to the memory cell array blocks having only good memory cells in response to at least one control signal.

4. The semiconductor memory device of claim 3, further comprising:

a control signal generator including a plurality of fuses, the fuses being adapted to be cut, for generating the at least one control signal when a corresponding fuse is cut;

wherein the selection signal generator includes a plurality of fuses, the fuses being adapted to be cut, for generating the selection signal when a corresponding fuse is cut.

5. A semiconductor memory device comprising:

a plurality of memory cell array blocks, wherein each memory cell array block comprises a plurality of memory cells, each memory cell being either good or defective;

address decoding circuitry for receiving and decoding a first address, decoding the first address to provide a plurality of address signals, the address signals corresponding to the first address;

a selection signal generator that generates a selection signal indicating which blocks have good memory cells and which blocks have at least one bad memory cell; and

a multiplexer responsive to the first address and the selection signal for generating an internal address signal;

wherein if the memory device has no memory cell array block having at least one defective memory cell, the internal address is the same as the first address, and if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is different from the first address.

6. The semiconductor memory device of claim 5, wherein if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is greater than the first address.

7. The semiconductor memory device of claim 6, wherein if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is greater than the first address by the number of memory cell array blocks having defective memory cells.

8. A method for addressing a plurality of memory cell array blocks in a semiconductor memory device, said method comprising:

determining which memory cell array blocks of the plurality of memory cell array blocks have at least one defective memory cell;

receiving a first address providing for access to one of the memory cell array blocks;

decoding the first address to provide a plurality of address signals, the address signals corresponding to the first address; and

generating a selection signal that indicates which memory cell array blocks have good memory cells and which memory cell array blocks have bad memory cells;

multiplexing the first address and the selection signal to generate an internal address;

wherein if the memory device has no memory cell array block having at least one defective memory cell, the internal address is the same as the first address, and if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is different from the first address.

9. The method of claim 8, wherein if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is greater than the first address.

10. The method of claim 9, wherein if the memory device has at least one memory cell array block having at least one defective memory cell, the internal address is greater than the first address by the number of memory cell array blocks having defective memory cells.