Semiconductor storage device

• US 6,188,628 B1
• Filed: 04/11/2000
• Issued: 02/13/2001
• Est. Priority Date: 04/13/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Tomotani, Hiroshi
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Ho, Hoai V.
• Application Number:
  US09/547,418
• Time in Patent Office: 308 Days
• Field of Search: 365/226, 365/227, 365/230.06, 365/189.01, 365/230.03
• US Class Current: 365/226
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

The semiconductor storage device of this invention includes a memory cell array; word lines; bit lines; a peripheral circuit for controlling the potentials of the word lines and the bit lines; a peripheral circuit power line for connecting a power voltage supply terminal to the peripheral circuit; a peripheral circuit power switch; a memory cell array power line; a constant voltage supply line for connecting the word lines to ground; a word line switch for fixing a voltage disposed on the constant voltage supply line; and the like. The potential of the word lines is fixed by controlling the word line switch to be placed in a conducting state before switching the peripheral circuit power switch. Thus, data in the memory cells can be prevented from being destroyed by a transient current caused in turning on/off the switch.

Claims

1. A semiconductor storage device comprising:

a power voltage supply part for supplying a power voltage;

a memory cell array connected to said power voltage supply part and including plural memory cells arranged in rows and columns;

plural word lines, for selecting a row to be accessed, each extending along each row of said memory cell arrays and connected to said memory cells of the row;

bit lines, for transferring data in a read operation or in a write operation, each extending along each column of said memory cell array and connected to said memory cells of the column;

a peripheral circuit for conducting a write operation or a read operation on said memory cells included in said memory cell array;

a peripheral circuit power line for connecting said memory as cell array to said peripheral circuit;

a peripheral circuit power switch disposed on said peripheral circuit power line to be changed between a conducting state and a non-conducting state in accordance with an activated state and an inactivated state of said peripheral circuit, respectively;

a constant voltage supply part for supplying a constant voltage within a range not affecting storage of data in said memory cells;

at least one constant voltage supply line for connecting said plural word lines to said constant voltage supply part; and

a voltage fixing switch disposed on said at least one constant voltage supply line to be changed between a non-conducting state and a conducting state in accordance with the activated state and the inactivated state of said peripheral circuit, respectively.

2. The semiconductor storage device of claim 1, further comprising a timing control circuit for controlling switching timing of said peripheral circuit power switch and said voltage fixing switch in response to an externally input standby signal, whereby said peripheral circuit power switch is kept in a conducting state before said voltage fixing switch changes between the conducting state and the non-conducting state.

3. The semiconductor storage device of claim 1, further comprising a word driver disposed in said peripheral circuit for driving said word lines,

wherein said voltage fixing switch is kept in the conducting state in synchronization with output of a high impedance data from said word driver.

4. The semiconductor storage device of claim 1,

wherein said word lines are directly connected to said memory cells, and

said constant voltage supply part is ground.

5. The semiconductor storage device of claim 1,

wherein said voltage fixing switch includes a MOS transistor having a gate electrode, a source electrode and a gate electrode,

one of said source electrode and said drain electrode is connected to said word lines and the other is connected to said constant voltage supply line, and

said gate electrode receives a signal for changing said voltage fixing switch between the conducting state and the non-conducting state.

6. The semiconductor storage device of claim 1,

wherein said voltage fixing switch includes a bipolar transistor having a base electrode, an emitter electrode and a collector electrode,

one of said emitter electrode and said collector electrode is connected to said word lines and the other is connected to said constant voltage supply line, and

said base electrode receives a signal for changing said voltage fixing switch between the conducting state and the non-conducting state.

7. The semiconductor storage device of claim 1,

wherein said constant voltage supply line and said voltage fixing switch are disposed on each of said plural word lines.

8. The semiconductor storage device of claim 1,

wherein said constant voltage supply line and said voltage fixing switch are shared by said plural word lines.

9. The semiconductor storage device of claim 1,

wherein said peripheral circuit includes MOS transistors having a given threshold voltage, and

each of said memory cells includes a MOS transistor having a threshold voltage higher than the given threshold voltage of said MOS transistors included in said peripheral circuit.

10. The semiconductor storage device of claim 1,

wherein said peripheral circuit includes MOS transistors having a given threshold voltage,

said peripheral circuit power switch includes a MOS transistor having a gate electrode, a source electrode and a drain electrode, and having a threshold voltage higher than the given threshold voltage of said MOS transistors included in said peripheral circuit,

one of said source electrode and said drain electrode is connected to said power voltage supply part and the other is connected to said peripheral circuit, and

said gate electrode receives a signal for changing said peripheral circuit power switch between the conducting state and the non-conducting state.

11. The semiconductor storage device of claim 1,

wherein said word lines include main word lines and plural sub word lines branched from each of said main word lines,

each of said sub word lines is provided with a sub word driver with inverted logic for driving the sub word line,

said constant voltage supply part is a power voltage supply terminal for supplying said power voltage, and

said constant voltage supply line is disposed between said main word lines and said power voltage supply terminal.

12. The semiconductor storage device of claim 11, further comprising a main word driver disposed in said peripheral circuit for driving said main word lines,

wherein said voltage fixing switch is kept in the conducting state in synchronization with output of a high impedance data from said main word driver.

13. The semiconductor storage device of claim 1,

wherein said word lines include main word lines and plural sub word lines branched from each of said main word lines,

each of said sub word lines is provided with a sub word driver with inverted logic for driving the sub word line,

said constant voltage supply part is ground, and

said constant voltage supply line is disposed between said sub word lines and said ground.

14. The semiconductor storage device of claim 13,

wherein said voltage fixing switch is placed in the conducting state in synchronization with output of a high impedance data from said sub word driver.