Integrated memory having column decoder for addressing corresponding bit line

• US 6,188,642 B1
• Filed: 07/06/1999
• Issued: 02/13/2001
• Est. Priority Date: 07/06/1998
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG)
• Original Assignee: Siemens AG
• Inventors: Dietrich, Stefan, Hein, Thomas, Marx, Thilo, Schrögmeier, Peter, Schöniger, Sabine
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/348,736
• Time in Patent Office: 588 Days
• Field of Search: 365/239, 365/233, 365/230.06, 365/236, 365/230.08, 371/21.2
• US Class Current: 365/239
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413

Abstract

The integrated memory has a column decoder for decoding column addresses and for addressing corresponding bit lines. The memory also has a first column address bus, which is used to transfer first column addresses to the column decoder, and a second column address bus, which is used to transfer second column addresses to the column decoder. The column decoder in each case addresses bit lines which correspond to the first and second column addresses supplied to it.

Claims

1. An integrated memory, comprising:

a column decoder for decoding column addresses and for addressing corresponding bit lines;

a first column address bus connected to said column decoder for transferring first column addresses to said column decoder;

a second column address bus connected to said column decoder for transferring second column addresses to said column decoder;

address input lines for receiving the first column addresses, said address input lines connected to said first column address bus for supplying the first column addresses thereto;

an address counter for storing and incrementing a starting address to obtain the second column addresses, said address counter connected to said second column address bus for supplying the second column addresses thereto during a specific number of clock cycles of a clock signal applied to said address counter; and

a control unit connected to said address input lines and to said address counter for loading one of the first column addresses into said address counter as the starting address;

said column decoder for addressing bit lines according to the first and second column addresses received through said first and second column buses respectively.

2. The memory according to claim 1, wherein the clock signal defines a second clock signal, the first column addresses are supplied from said first column address bus to said column decoder in dependence on a first clock signal, and the second column addresses are supplied from said second column address bus to said column decoder in dependence on the second clock signal.

3. The memory according to claim 2,

wherein said address counter is controlled by the second clock signal.

4. The memory according to claim 3, wherein said control unit for loading the starting address into said address counter is controlled by the first clock signal.

5. The memory according to claim 4, which further comprises a plurality of word lines and a row decoder for addressing said word lines;

wherein said first column address bus is also a row address bus usable, with time-division multiplexing to transfer the first column addresses, for additionally transferring row addresses from said address inputs to said row decoder for addressing said word lines; and

wherein the row addresses are supplied from said first column address bus to said row decoder in dependence on a third clock signal.