Clock extraction circuit

• US 6,188,738 B1
• Filed: 03/13/1998
• Issued: 02/13/2001
• Est. Priority Date: 10/16/1997
• Status: Expired due to Fees

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Sugata, Akihiko, Sakamoto, Hisaya, Kiyonaga, Tetsuya, Miyazaki, Akimitsu
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Rupert, Paul N
• Application Number:
  US09/041,777
• Time in Patent Office: 1,068 Days
• Field of Search: 327/165, 375/371, 375/359, 375/360, 375/361, 375/355, 375/214, 375/317, 369/124
• US Class Current: 375/371
• CPC Class Codes: H04B 10/66 Non-coherent receivers, e.g. using direct detection
• CPC Class Codes: H04L 7/027 extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

Disclosed is a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal. The clock extraction circuit has a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data. The data signal is input to the timing extraction unit via the filter.

Claims

1. A clock extraction circuit for extracting a clock signal, which furnishes timing for discriminating a data signal, from the data signal, comprising:

a timing extraction unit to extract the clock signal from the data signal; and

a filter having an upper limited frequency sufficiently lower than the bit rate of the data;

wherein the data signal is input to said timing extraction unit via said filter.

2. A clock extraction circuit for extracting a clock signal, which furnishes timing for discriminating a data signal, from the data signal, comprising:

a timing extraction unit to extract the clock signal from the data signal; and

a slicer amplifier to vary slice level to improve the duty cycle of the data signal;

wherein the data signal is input to said timing extraction unit via said slicer amplifier.

3. The circuit according to claim 2, further comprising:

a mean-value circuit to output a mean value of an output from said slicer amplifier; and

a feedback circuit to control the slice level based upon the mean value to improve the duty cycle of the data signal.

4. The circuit according to claim 2, further comprising:

an AND gate to obtain the logical product of an output from said slicer amplifier and the extracted clock output by said timing extraction unit;

a mean-value circuit to output a mean value of an output from said AND gate; and

a feedback circuit to control the slice level based upon the mean value to improve the duty cycle of the data signal.

5. The circuit according to claim 2, further comprising:

a filter, which has an upper limited frequency sufficiently lower than the bit rate of the data;

wherein the data signal is input to said slicer amplifier via said filter.

6. The circuit according to claim 5, further comprising:

a mean-value circuit to output a mean value of an output from said slicer amplifier; and

a feedback circuit to control the slice level based upon the mean value to improve the duty cycle of the data signal.

7. The circuit according to claim 5, further comprising:

an AND gate to obtain the logical product of an output from said slicer amplifier and the extracted clock output by said timing extraction unit;

a mean-value circuit to output a mean value of an output from said AND gate; and

a feedback circuit to control the slice level based upon the mean value to improve the duty cycle of the data signal.