Fast technique for converting temperature readings into values expressed in an engineering unit format

• US 6,188,971 B1
• Filed: 05/28/1999
• Issued: 02/13/2001
• Est. Priority Date: 11/15/1991
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Kelly, Christopher P. J.
• Primary Examiner(s): Hoff, Marc S.
• Assistant Examiner(s): VO, HIEN XUAN
• Application Number:
  US09/322,474
• Time in Patent Office: 627 Days
• Field of Search: 702/130, 702/198, 702/85, 702/99, 340/870.21, 340/870.05, 341/106
• US Class Current: 702/130
• CPC Class Codes: G01D 3/022 having an ideal characteristic, map or correction data stored in a digital memory
• CPC Class Codes: G01D 3/0365 the undesired influence being measured using a separate sensor, which produces an influence related signal
• CPC Class Codes: G01K 1/028 arrangements for numerical indication
• CPC Class Codes: G01K 2219/00 Thermometers with dedicated analog to digital converters

Abstract

An engineering unit converter system for converting an analog measurement into an engineering value. An analog measurement of a physical quantity is transformed into a digital value. The digital value is then split into a high order digit and a lower order digit. The high order digit is used as an address to a memory device for fetching a line segment coefficient and a line segment offset coefficient. The lower order digit is multiplied with the line segment coefficient in a multiplier resulting in a product. The product is added to the line segment coefficient offset resulting in a sum whose value is an engineering unit. One embodiment is directed to converting temperature measurements into engineering units via thermocouples. This embodiment includes: thermocouple devices, resistance thermal devices or positive temperature coefficient thermistors, adders, multipliers, and memory devices (readable and writable memory devices).

Claims

1. A system for converting a temperature reading into a value expressed in an engineering unit format, said system comprising:

a thermocouple for converting said temperature reading into a first voltage reading;

an analog-to-digital converter for converting said first voltage reading into a first digital value;

at least one memory device for storing a plurality of first coefficients, a plurality of second coefficients, and a plurality of reference coefficients;

a sequencer for enabling fetching of a first coefficient, a second coefficient, and a reference coefficient from said plurality of first coefficients, said plurality of second coefficients, and said plurality of reference coefficients stored in said at least one memory device;

a first adder for subtracting said fetched reference coefficient from said first digital value, thereby producing a second digital value having low order bits and high order bits;

a multiplier for multiplying a number identified by said low order bits, and said fetched first coefficient, thereby producing a product; and

a second adder for adding said product to said fetched second coefficient, thereby producing said value expressed in an engineering unit format;

wherein a reference temperature is used to address said at least one memory device when said sequencer fetches said reference coefficient, and said high order bits are used to address said at least one memory device when said sequencer fetches said first coefficient and said second coefficient.

2. A system as in claim 1, further comprising:

a wiring junction block, wherein said first voltage reading is provided to said analog-to-digital converter via said wiring junction block; and

a thermistor for acquiring a temperature of said wiring junction block and converting said wiring junction block temperature into a second voltage reading;

wherein said analog-to-digital converter converts said second voltage reading into a third digital value, said third digital value being indicative of said reference temperature.

3. A system as in claim 1, further comprising:

a wiring junction block, wherein said first voltage reading is provided to said analog-to-digital converter via said wiring junction block; and

a resistance thermal device for acquiring a temperature of said wiring junction block and converting said wiring junction block temperature into a second voltage reading;

wherein said analog-to-digital converter converts said second voltage reading into a third digital value, said third digital value being indicative of said reference temperature.

4. A system as in claim 1, further comprising:

a wiring junction block, wherein said first voltage reading is provided to said analog-to-digital converter via said wiring junction block; and

a positive temperature coefficient thermistor for acquiring a temperature of said wiring junction block and converting said wiring junction block temperature into a second voltage reading;

wherein said analog-to-digital converter converts said second voltage reading into a third digital value, said third digital value being indicative of said reference temperature.

5. A system as in claim 1, wherein:

said sequencer receives an actuation signal from said analog-to-digital converter; and

said fetching enabled by said sequencer is begun in response to said sequencer'"'"'s receipt of said actuation signal.

6. A system as in claim 1, wherein a sensor type signal is used to select a table within said at least one memory device, said table corresponding to the type of said thermocouple.

7. A system as in claim 1, wherein said multiplier and second adder are controlled by said sequencer.

8. A system as in claim 1, wherein said multiplier and second adder are floating point devices.

9. A system as in claim 8, further comprising an additional memory device for storing a floating point look-up table, wherein:

said low order bits serve as an address for retrieving a floating point coefficient from said floating point look-up table; and

said floating point coefficient is said number identified by said low order bits.

10. A system as in claim 1, wherein:

said at least one memory device comprises a first memory device and a second memory device;

said first memory device is configured to store said plurality of first coefficients; and

said second memory device is configured to store said plurality of second coefficients.

11. A system as in claim 10, further comprising a pipeline address control, under control of said sequencer, for providing addresses to said first and second memory devices so as to enable simultaneous processing of data fetched from said first and second memory devices.

12. A system as in claim 11, wherein said multiplier and second adder are floating point devices, further comprising an additional memory device for storing a floating point look-up table, wherein:

said low order bits serve as an address for retrieving a floating point coefficient from said floating point look-up table; and

said floating point coefficient is said number identified by said low order bits.

13. A system as in claim 11, wherein said multiplier and second adder are integer devices.

14. A system as in claim 10, wherein said multiplier and second adder are floating point devices, further comprising an additional memory device for storing a floating point look-up table, wherein:

said low order bits serve as an address for retrieving a floating point coefficient from said floating point look-up table; and

said floating point coefficient is said number identified by said low order bits.

15. A system as in claim 10, wherein said multiplier and second adder are integer devices.

16. A system as in claim 1, wherein said multiplier and second adder are integer devices.

17. A system as in claim 1, wherein each of said at least one memory device is a random access memory device.

18. A system as in claim 1, wherein said number identified by said low order bits is equivalent to said low order bits.

19. A system for converting a temperature reading into a value expressed in an engineering unit format, said system comprising:

a thermocouple measurement set-up providing a first voltage reading which is indicative of said temperature reading, and a second voltage reading which is indicative of a reference temperature;

an analog-to-digital converter for converting said first voltage reading into a first digital value, and converting said second voltage reading into a second digital value;

at least one memory device for storing a plurality of first coefficients, a plurality of second coefficients, and a plurality of reference coefficients;

a sequencer for enabling fetching of a first coefficient, a second coefficient, and a reference coefficient from said plurality of first coefficients, said plurality of second coefficients, and said plurality of reference coefficients stored in said at least one memory device;

a first adder for subtracting said fetched reference coefficient from said first digital value, thereby producing a third digital value having low order bits and high order bits;

a multiplier for multiplying a number identified by said low order bits and said fetched first coefficient, thereby producing a product; and

a second adder for adding said product to said fetched second coefficient, thereby producing said value expressed in an engineering unit format;

wherein said second digital value is used to address said at least one memory device when said sequencer fetches said reference coefficient, and said high order bits are used to address said at least one memory device when said sequencer fetches said first coefficient and said second coefficient.

20. A method of compensating for thermoelectric effects of an intermediate wiring junction when converting a temperature reading into a value expressed in an engineering unit format, said method comprising:

acquiring a reference temperature, said reference temperature being indicative of a temperature of said intermediate wiring junction;

converting said temperature reading into a first digital value, and converting said reference temperature into a second digital value;

using said second digital value to address a reference coefficient stored in a memory;

subtracting said reference coefficient from said first digital value, thereby producing a third digital value;

splitting said third digital value into low order bits and high order bits;

using said high order bits to address first and second coefficients stored in said memory;

multiplying a number identified by said low order bits and said first coefficient, thereby producing a product; and

adding said product to said second coefficient, thereby producing said value expressed in an engineering unit format.

21. A method as in claim 20, wherein manipulations of said first, second and third digital values are performed by a computer, and said steps of addressing, multiplying and adding are controlled by a sequencer in said computer.