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Method and apparatus for interrupt load balancing for powerPC processors

  • US 6,189,065 B1
  • Filed: 09/28/1998
  • Issued: 02/13/2001
  • Est. Priority Date: 09/28/1998
  • Status: Expired due to Fees
First Claim
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1. A method for servicing an interrupt message in a data processing system having a plurality of processors, comprising the steps of:

  • mapping special Purpose registers in each of said plurality of processors wherein said mapping logic provides, at least;

    a receive port register for holding a unique address for said processor;

    a signal pending buffer for holding a bit location;

    at least two masking registers for said interrupt message;

    a next processor register for designating a successive processor to receive an interrupt;

    directing said interrupt message to a first processor;

    masking said interrupt message to determine said interrupt message priority;

    storing, in an interrupt source register, the address of the highest priority qeued said interrupt message;

    utilizing the contents of said signal pending buffer and said at least two masking registers for determining the interrupts that are queued in said first processor;

    utilizing an offload selector for offloading a specific (said interrupt message to a processor specified in said next processor register if said first processor is busy servicing another interrupt; and

    offloading said interrupt message from each successive busy processor to a different processor specified in said busy processor'"'"'s next processor register until said interrupt message is accepted by one of said plurality of processors.

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