Method and apparatus for interrupt load balancing for powerPC processors

• US 6,189,065 B1
• Filed: 09/28/1998
• Issued: 02/13/2001
• Est. Priority Date: 09/28/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arndt, Richard Louis, Chen, Wen-Tzer Thomas
• Primary Examiner(s): Lefkowitz, Sumati
• Application Number:
  US09/161,622
• Time in Patent Office: 869 Days
• Field of Search: 710/260-269, 709/102-108
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 2213/2412 Dispatching of interrupt load among interrupt handlers in processor system or interrupt controller
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/505 considering the load

Abstract

Interrupts from an I/O subsystem are first directed to a single processor in a multiple superscalar processor data processing system. If an interrupt load on the processor is sufficiently high, the interrupt is sent (offloaded) to a second specific processor. The process continues throughout all superscalar processors in the data processing system and each processor builds interrupt prediction data corresponding to the interrupt load. A threshold counter may be added to the logic so offloading does not take place until a specified number of interrupts are queued within that specific processor, thus providing a fixed level of prediction data. Some processors may be left out of the offload string so they are not disturbed by an interrupt.

Claims

1. A method for servicing an interrupt message in a data processing system having a plurality of processors, comprising the steps of:

mapping special Purpose registers in each of said plurality of processors wherein said mapping logic provides, at least;

a receive port register for holding a unique address for said processor;

a signal pending buffer for holding a bit location;

at least two masking registers for said interrupt message;

a next processor register for designating a successive processor to receive an interrupt;

directing said interrupt message to a first processor;

masking said interrupt message to determine said interrupt message priority;

storing, in an interrupt source register, the address of the highest priority qeued said interrupt message;

utilizing the contents of said signal pending buffer and said at least two masking registers for determining the interrupts that are queued in said first processor;

utilizing an offload selector for offloading a specific (said interrupt message to a processor specified in said next processor register if said first processor is busy servicing another interrupt; and

offloading said interrupt message from each successive busy processor to a different processor specified in said busy processor'"'"'s next processor register until said interrupt message is accepted by one of said plurality of processors.

2. The method of claim 1, wherein said step of directing an interrupt signal to a first processor further comprises

transmitting said interrupt message via an interrupt source controller to said processor; and

storing the source address of said interrupt message on board said processor.

3. The method in claim 1, wherein said step of utilizing said offload selector for offloading a specific said interrupt message to a processor specified in said next processor register if said first processor is busy servicing another interrupt message, further comprises:

pre-determining a specific number of interrupts each processor will manage prior to offloading additional interrupts to a second processor.

4. The method in claim 1, further comprising storing interrupt prediction data in each processor.

5. The method in claim 1, further comprising the step of

transmitting said interrupt signal directly from a data processing system component.

6. The method in claim 1, wherein said step of offloading said interrupt message from each successive busy processor to a different processor specified in said busy processor'"'"'s next processor register until said interrupt message is accepted by one of said plurality of processors further comprises:

pre-designating a receiving order of said plurality of processors to which interrupt signals will be directed;

limiting a number of interrupt signals that each one of said plurality of processors will manage prior to offloading additional interrupts to a specified second processor, by including a threshhold counter; and

offloading said additional interrupts to each of said plurality of processors in said receiving order.

7. A data processing system having a plurality of processors, comprising:

logic within each processor for mapping special purpose registers wherein said mapped registers comprise, at least;

a receive report register for holding a unique address for said processor;

a signal pending buffer for holding a bit corresponding to an interrupt message address source;

at least two masking registers for masking said interrupt message to determine said interrupt message priority;

a next processor register for designating a next processor in line to receive an interrupt;

means for directing an interrupt message to a first processor;

an interrupt source register for storing the address of the highest priority queued said interrupt message;

an offload selector for offloading said interrupt message to another processor if said first processor is busy servicing another interrupt signal; and

means for offloading said interrupt message from each said busy processor to a processor, specified in said busy processor'"'"'s next processor register, within said data processing system until said interrupt signal is accepted by one of said plurality of processors.

8. The data processing system of claim 7, wherein said an offload selector for offloading said interrupt message to a second processor if said first processor is busy servicing another interrupt signal further comprises:

logic means for pre-designating a second processor for receiving an interrupt signal if said first processor is busy; and

logic containing a threshhold counter for predetermining a specific number of interrupts for each processor to manage prior to offloading additional interrupts to said second processor.

9. The data processing system of claim 7, further comprising

a mapped register onboard said processor for storing interrupt message prediction data.

10. The data processing system of claim 8, further comprising

a means for receiving an external interrupt message directly from a data processing system component.

11. The data processing system of claim 7, wherein said means for offloading said interrupt message to each of said plurality of processors until said interrupt message is accepted by one of said processors further comprises:

means for pre-designating a receiving order of said plurality of processors that will receive interrupts;

a threshhold counter for limiting a number of interrupt messages that each one of said plurality of processors will manage prior to offloading additional interrupts to a specified second processor; and

logic means for successively offloading said additional interrupts to each of said plurality of processors.

12. A computer-readable medium for servicing an interrupt message in a data processing system having a plurality of processors, comprising:

instructions within said computer-readable medium for mapping special purpose registers in each of said plurality of processors wherein said mapping logic provides, at least;

a receive port register for holding a unique address for said processor;

a signal pending buffer for holding a bit location;

at least two masking registers for said interrupt message;

a next Processor register for designating a successive processor to receive an interrupt;

instructions within said computer-readable medium for directing said interrupt message to a first processor;

instructions within said computer-readable medium for masking said interrupt message to determine said interrupt message priority;

instructions within said computer-readable medium for storing, in an interrupt source register, the address of the highest priority queued said interrupt message;

instructions within said computer-readable medium for utilizing the contents of said signal pending buffer and said at least two masking registers for determining the interrupts that are queued in said first processor;

instructions within said computer-readable medium for utilizing an offload selector for offloading a specific said interrupt message to a processor specified in said next processor register if said first processor is busy servicing another interrupt; and

instructions within said computer-readable medium for offloading said interrupt message from each successive busy processor to a different processor within said data processing system until said interrupt message is accepted by one of said plurality of processors.

13. The computer-readable medium of claim 12, wherein said instructions for directing an interrupt message to a first processor further comprises

instructions within said computer-readable medium for transmitting said interrupt message via an interrupt source controller to said processor; and

instructions within said computer-readable medium for storing the source address of said interrupt message on board said first processor.

14. The computer-readable medium of claim 12, wherein said instructions for offloading said interrupt message if said first processor is busy servicing another interrupt message further comprises:

instructions within the computer-readable medium for predetermining a specific number of interrupts for each processor to manage prior to offloading additional interrupts to a second processor.

15. The computer-readable medium of claim 12, further comprising

instructions within the computer-readable medium for storing interrupt prediction data in each processor.

16. The computer-readable medium of claim 12, further comprising

instructions within the computer-readable medium for transmitting said interrupt message directly from a data processing system component.

17. The computer-readable medium of claim 12, wherein said instructions for offloading said interrupt message to each of said plurality of processors until said interrupt message is accepted by one of said processors further comprises:

instructions within the computer-readable medium for predesignating a receiving order of said plurality of processors that will receive interrupts;

instructions within the computer-readable medium for limiting a number of interrupt messages that each one of said plurality of processors will manage prior to offloading additional interrupts to a specified second processor, by including a threshold counter; and

instructions within the computer-readable medium for successively offloading said additional interrupts to each of said plurality of processors.