Mechanism for storing system level attributes in a translation lookaside buffer

• US 6,189,074 B1
• Filed: 03/19/1997
• Issued: 02/13/2001
• Est. Priority Date: 03/19/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pedneau, Michael
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Anderson, Matthew D.
• Application Number:
  US08/820,965
• Time in Patent Office: 1,427 Days
• Field of Search: 711/117, 711/205, 711/207, 711/208, 711/100, 711/206, 711/144, 711/201, 711/203, 711/204, 711/136, 711/139, 711/145, 711/202, 340/825.52, 340/825.53, 345/188, 345/193, 345/197, 345/198, 345/513, 345/516, 345/846
• US Class Current: 711/139
• CPC Class Codes: G06F 12/1045 associated with a data cache

Abstract

A method and apparatus for improving the efficiency of the cacheability (and other attribute) determination by making the information from the region register available during linear to physical address translation, rather than serially upon completion of the address translation. Address range comparisons are made when the TLB is loaded. That is, attribute information stored in a region register or registers is compared with physical addresses corresponding to translations loaded in a translation lookaside buffer reload operation. The present invention thus advantageously removes the region register compare operation from the path to memory.

Claims

1. A computer system comprising:

a bus;

a main memory operatively coupled to the bus;

a processor coupled to the bus, wherein the processor includes a translation lookaside buffer and a first region register, wherein the translation lookaside buffer includes a plurality of translation entries, wherein each of the translation entries is configured to store a linear address tag, a page frame base address and a cacheability indicator, wherein the translation lookaside buffer is configured to receive a linear address,

wherein, in response to the linear address hitting a first translation entry of the plurality of translation entries, the processor is configured to;

(a) generate a first physical address using an offset portion of the linear address and a first page frame base address of the first translation entry, and (b) concurrently determine a cacheability of data corresponding to said linear address responsive to a first cacheability indicator read from the first translation entry;

and wherein, in response to the linear address missing in the translation lookaside buffer, the processor is configured to;

(a) locate a translation corresponding to the linear address within a plurality of page tables in the main memory, the translation defining a second page frame base address corresponding to the linear address, (b) compare the second page frame base address with a physical address region defined by the first region register, the first region register further defining a cacheability of the physical address region independent of said translation, (c) assign a second cacheability indicator according to said cacheability defined in said first region register if said second page frame base address is within the physical address region defined by said first region register, and (d) store the second page frame base address and the second cacheability indicator in one of the plurality of translation entries.

2. The computer system of claim 1, wherein, in response to storing the second page frame base address and the second cacheability indicator in said one of the plurality of translation entries, the processor is further configured to generate a second physical address using the offset portion of the linear address and the second page frame base address, and wherein the second cacheability indicator controls whether or not data corresponding to the linear address is cacheable.

3. The computer system of claim 1, wherein the second page frame base address and second cacheability indicator are stored in said one of the plurality of translation entries according to a least recently used allocation policy.

4. The computer system of claim 1, wherein each of the plurality of translation entries includes a region attributes field, wherein the region attributes field stores a plurality of attributes including the cacheability indicator, wherein the processor is configured to assign the plurality of attributes in response to said comparison of the second page frame base address with the physical address region defined by the first region register.

5. The computer system of claim 1 wherein the physical address region defined by the first region register includes at least two memory pages.

6. A method for providing cacheability information:

receiving a linear address;

comparing the linear address to a plurality of translation entries stored in a translation lookaside buffer, wherein each of the plurality of translation entries stores a linear address tag, a page frame base address and a cacheability indicator;

in response to the linear address hitting a first translation entry of the plurality of translation entries, (a) generating a first physical address using an offset portion of the linear address and a first page frame base address of the first translation entry, and (b) concurrently determining a cacheability of data corresponding to said linear address responsive to a first cacheability indicator read from the first translation entry;

in response to the linear address missing in the translation lookaside buffer, (a) locating a translation corresponding to the linear address within a plurality of page tables in a main memory, the translation defining a second page frame base address corresponding to the linear address, (b) comparing the second page frame base address with a physical address region defined by a first region register, the first region register further defining a cacheability of the physical address region independent of said translation, (c) assigning a second cacheability indicator according to said cacheability defined in said first region register if said second page frame base address is within the physical address region defined by said first region register, and (d) storing the second page frame base address and the second cacheability indicator in one of the plurality of translation entries.

7. The method of claim 6, further comprising generating a second physical address using the offset portion of the linear address and the second page frame base address, wherein the second cacheability indicator controls whether or not data corresponding to the linear address is cacheable.

8. The method of claim 6, wherein said storing of the second page frame base address and the second cacheability indicator in said one of the plurality of translation entries operates according to a least recently used allocation policy.

9. The method of claim 6, wherein each of the plurality of translation entries includes a region attributes field, wherein the region attributes field stores a plurality of attributes including the cacheability indicator, wherein the processor assigns the plurality of attributes in response to said comparing of the second page frame base address and the physical address region defined by the first region register.

10. The method as recited in claim 6 wherein the address region defined by the region register includes at least two memory pages.

11. A processor comprising a translation lookaside buffer and a first region register, wherein the translation lookaside buffer includes a plurality of translation entries, wherein each of the translation entries is configured to store a linear address tag, a page frame base address and a cacheability indicator, wherein the translation lookaside buffer is configured to receive a linear address;

wherein, in response to the linear address hitting a first translation entry of the plurality of translation entries, the processor is configured to;

(a) generate a first physical address using an offset portion of the linear address and a first page frame base address of the first translation entry, and (b) concurrently determine a cacheability of data corresponding to said linear address responsive to a first cacheability indicator read from the first translation entry;

and wherein, in response to the linear address missing in the translation lookaside buffer, the processor is configured to;

(a) locate a translation corresponding to the linear address within a plurality of page tables in a main memory, the translation defining a second page frame base address corresponding to the linear address, (b) compare the second page frame base address with a physical address region defined by the first region register, the first region register further defining a cacheability of said physical address region independent of said translation, (c) assign a second cacheability indicator according to said cacheability defined in said first region register if said second page frame base address is within the physical address region defined by said first region register, and (d) store the second page frame base address and the second cacheability indicator in one of the plurality of translation entries.

12. The processor of claim 11, wherein, in response to storing the second page frame base address and the second cacheability indicator in said one of the plurality of translation entries, the processor is further configured to generate a second physical address using the offset portion of the linear address and the second page frame base address, and wherein the second cacheability indicator controls whether or not data corresponding to the linear address is cacheable.

13. The processor of claim 11, wherein the second page frame base address and second cacheability indicator are stored in said one of the plurality of translation entries according to a least recently used allocation policy.

14. The processor of claim 11, wherein each of the plurality of translation entries includes a region attributes field, wherein the region attributes field stores a plurality of attributes including the cacheability indicator, wherein the processor is configured to assign the plurality of attributes in response to said comparison of the second page frame base address with the physical address region defined by the first region register.

15. The processor of claim 11 wherein the physical address region defined by the first region register includes at least two memory pages.