Apparatus and method for retiring instructions in excess of the number of accessible write ports

• US 6,189,089 B1
• Filed: 01/06/1999
• Issued: 02/13/2001
• Est. Priority Date: 07/24/1996
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Walker, Wade A., Matheny, D. T.
• Primary Examiner(s): Follansbee, John A.
• Assistant Examiner(s): Whitmore, Stacy
• Application Number:
  US09/227,505
• Time in Patent Office: 769 Days
• Field of Search: 712/1-43, 712/200-248, 712/300
• US Class Current: 712/218
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A superscalar microprocessor includes a reorder buffer to correctly handle dependency checking and multiple updates to the same destination. The reorder buffer stores instructions in program order, and retires instructions that have executed and the results obtained. When a instruction is retired, the results of the instruction are stored and the memory space in the reorder buffer is deallocated. The results of the retired instructions are stored to a register file via a retire bus. If the results of two or more retired instructions output to the same register in the register file, then only the newest instruction, the later instruction in the original program sequence, is stored to the program register. The register file has a plurality of write ports for the transfer of data via the retire bus. If two retired instructions output to the same register, then a write port is not utilized. The retire window is the number of instructions monitored for retirement. The present invention advantageously increases the size of the retire window. Accordingly, if two or more retired instructions output to the same register, an additional instruction from the retire window can be retired. The additional instruction utilizes the write port not used by the older of the instructions that output to the same register. Thereby, the reorder buffer is emptied at a faster rate and causes less instruction dispatch stalls.

Claims

1. A reorder buffer comprising:

an instruction storage device, wherein said instruction storage device is configured to store instruction results corresponding to a plurality of instructions, and wherein each of said plurality of instructions includes a register operand that corresponds to a register in a register file having a plurality of write ports; and

a control unit coupled to said instruction storage device, wherein said control unit is configured to select a subset of said plurality of instructions for retirement during a clock cycle;

wherein a number of instructions retired during said clock cycle exceeds a total number of said plurality of write ports of said register file.

2. The reorder buffer as recited in claim 1, wherein said subset of said plurality of instructions comprises a retirement window.

3. The reorder buffer as recited in claim 1, wherein said control unit is configured to update one or more registers in said register file corresponding to one or more of said register operands within said subset of said plurality of instructions;

and wherein if two or more register operands within said subset of said plurality of instructions correspond to a same register in said register file, said control unit is configured to update said same register using only a newest, in program order, of said two or more register operands.

4. The reorder buffer as recited in claim 1, wherein said instruction storage device is configured to store a set of bits corresponding to each of said plurality of instructions;

wherein said control unit is configured to determine a newest, in program order, of two or more register operands within said subset of said plurality of instructions that correspond to a same register in said register file using said set of bits; and

wherein if two or more register operands within said subset correspond to a same register in said register file, said control unit is configured to update said same register using only said newest, in program order, of said two or more register operands.

5. The reorder buffer as recited in claim 4, wherein a number of bits in said set of bits is equal to said total number of write ports in said register file.

6. The reorder buffer as recited in claim 1, wherein said subset of said plurality of instructions includes instructions that have completed execution and obtained a result.

7. The reorder buffer as recited in claim 6, wherein said control unit is configured to assign each instruction within said subset of said plurality of instructions to a write port of said register file, and wherein said control unit is configured not to assign instructions within said subset that are older than another instruction within said subset that corresponds to a same register.

8. An apparatus for retiring instructions, comprising:

a register file, wherein said register file includes a plurality of registers, and wherein said register file includes a plurality of write ports; and

a reorder buffer coupled to said register file, wherein said reorder buffer includes;

an instruction storage device, wherein said instruction storage device is configured to store instruction results corresponding to a plurality of instructions, and wherein each of said plurality of instructions includes a register operand that corresponds to one of said plurality of registers; and

a control unit coupled to said instruction storage device, wherein said control unit is configured to select a subset of said plurality of instructions for retirement during a clock cycle;

wherein a number of instructions in said subset exceeds a total number of said plurality of write ports of said register file.

9. The apparatus as recited in claim 8, wherein said subset of said plurality of instructions comprises a retirement window.

10. The apparatus as recited in claim 8, wherein said control unit is configured to update one or more of said plurality of registers corresponding to one or more of said register operands within said subset of said plurality of instructions;

and wherein if two or more register operands within said subset of said plurality of instructions correspond to a same register, said control unit is configured to update said same register using only a newest, in program order, of said two or more register operands.

11. The apparatus as recited in claim 8, wherein said instruction storage device is configured to store a set of bits corresponding to each of said plurality of instructions;

wherein said control unit is configured to determine a newest, in program order, of two or more register operands within said subset of said plurality of instructions that correspond to a same register in said plurality of registers using said set of bits; and

wherein if two or more register operands within said subset of said plurality of instructions correspond to a same register, said control unit is configured to update said same register using only said newest, in program order, of said two or more register operands.

12. The apparatus as recited in claim 11, wherein a number of bits in said set of bits is equal to said total number of write ports in said register file.

13. The apparatus as recited in claim 8, wherein said subset of said plurality of instructions includes instructions that have completed execution and obtained a result.

14. The apparatus as recited in claim 13, wherein said control unit is configured to assign each instruction within said subset of said plurality of instructions to a write port of said register file, wherein said control unit is configured not to assign instructions within said subset that are older than another instruction within said subset that corresponds to a same register.

15. A method for retiring instructions in a reorder buffer, the method comprising:

storing, in said reorder buffer, instruction results corresponding to a plurality of instructions, wherein each of said plurality of instructions include a register operand that corresponds to a register in a register file;

selecting a subset of said plurality of instructions for retirement during a clock cycle, wherein a number of instructions in said subset exceeds a total number of write ports of said register file; and

retiring said subset of said plurality of instructions during said clock cycle.

16. The method as recited in claim 15, wherein said subset of said plurality of instructions comprises a retirement window.

17. The method as recited in claim 15, further comprising:

updating one or more registers in said register file corresponding to said register operands within said subset of said plurality of instructions; and

if two or more register operands within said subset of said plurality of instructions correspond to a same register, updating said same register using only a newest, in program order, of said two or more register operands.

18. The method as recited in claim 15, further comprising:

determining a newest, in program order, instruction within said subset of said plurality of instructions to update a register using a set of bits attached to each instruction in said retirement window; and

if two or more register operands within said subset of said plurality of instructions correspond to a same register, updating said same register using only a newest, in program order, of said two or more register operands.

19. The method as recited in claim 18, wherein a number of bits in said set of bits is equal to said total number of write ports in said register file.

20. The method as recited in claim 15, further comprising:

assigning each instruction in said subset of said plurality of instructions to a write port of said register file, wherein each instruction in said subset of said plurality of instructions that is older than another instruction in said subset of said plurality of instructions and that corresponds to a same register are not assigned to a write port.