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Formation of 5F2 cell with partially vertical transistor and gate conductor aligned buried strap with raised shallow trench isolation region

  • US 6,190,971 B1
  • Filed: 05/13/1999
  • Issued: 02/20/2001
  • Est. Priority Date: 05/13/1999
  • Status: Expired due to Term
First Claim
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1. A method of manufacturing an integrated circuit chip comprising:

  • forming an opening having at least one step in a substrate;

    forming a first conductor in said opening below said step;

    forming a first diffusion region in said substrate adjacent said first conductor and below said step;

    forming a gate conductor over said step and in said opening;

    forming a second conductor over said substrate adjacent said gate conductor; and

    forming a second diffusion region in said substrate adjacent said second conductor.

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