Method for fabricating lateral RF MOS devices with enhanced RF properties

• US 6,190,978 B1
• Filed: 04/16/1999
• Issued: 02/20/2001
• Est. Priority Date: 05/04/1998
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Xemod, Inc. (Qorvo, Inc.)
• Inventors: D'Anna, Pablo Eugenio
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H
• Application Number:
  US09/293,431
• Time in Patent Office: 676 Days
• Field of Search: 438/301, 438/303, 438/197
• US Class Current: 438/301
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of fabrication of a lateral RF MOS device having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure. In another embodiment, the lateral RF MOS device has a quasi-mesh silicided gate structure. Both sides of each gate are oxidized thus preventing possible shorts between source and gate regions and between drain and gate regions. The top of each gate is silicided once the protective layer of silicon nitride is removed.

Claims

1. A method of forming a lateral RF MOS device with a non-diffusion source-substrate connection, starting from a substrate, said method comprising the steps of:

providing a semiconductor substrate having a principle surface and being of a first conductivity type;

growing an epi silicon layer on a top surface of said substrate, said epi layer having a first conductivity type;

growing a field oxide layer on a top surface of said epi layer, wherein the field oxide layer comprises a silicon nitride layer and a first oxide layer;

removing a part of said silicon nitride layer and a part of said first oxide layer from an active device area;

growing a gate oxide layer in said active device area;

making deposit of a polysilicon layer;

making a deposit of a second silicon nitride layer;

using a second mask on said polysilicon layer and said second silicon nitride layer to make a pattern gate structure;

oxidizing selectively sides of said gate structure;

removing a top part of said second silicon nitride layer;

depositing a siliciding metal selected from the group consisting of platinum, cobalt, tungsten, and titanium;

heating to form the metal silicided layer;

removing the unsilicided metal;

forming a plurality of gate channels;

forming a plurality of drain regions and a plurality of source regions;

forming a silicided layer on said gate structure; and

forming a plurality of metal contacts for connecting said plurality of gate channels, said plurality of drain regions and said plurality of source regions with an outside circuitry.