Method of improving copper pad adhesion

• US 6,191,023 B1
• Filed: 11/18/1999
• Issued: 02/20/2001
• Est. Priority Date: 11/18/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Sheng-Hsiung
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/442,497
• Time in Patent Office: 460 Days
• Field of Search: 257/782, 257/784, 257/774, 257/751, 438/118, 438/617, 438/629, 438/637, 438/627, 438/612, 438/618, 438/622, 438/625
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05559 non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48458 of the interface with the bonding area
• CPC Class Codes: H01L 2224/4847 the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48724 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48799 Principal constituent of the connecting portion of the wire connector being Copper (Cu)
• CPC Class Codes: H01L 2224/48824 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/859 involving monitoring, e.g. feedback loop
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/20753 : larger or equal to 30 microns less than 40 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

This invention relates to a new improved method and structure in the fabricating of aluminum metal pads. The formation special aluminum bond pad metal structures are described which improve adhesion between the tantalum nitride pad barrier layer and the underlying copper pad metallurgy by a special interlocking bond pad structure. It is the object of the present invention to provide a process wherein a special grid of interlocking via structures is placed in between the underlying copper pad metal and the top tantalum nitride pad barrier layer providing improved adhesion to the aluminum pad metal stack structure. This unique contact bond pad structure provides for thermal stress relief, improved wire bond adhesion to the aluminum pad, and prevents peeling during wire bond adhesion tests.

Claims

1. A method of fabricating an integrated circuit and other devices on a substrate, the method comprising the following steps:

providing a substrate;

providing said substrate with a layer of dielectric, termed an interlevel dielectric (ILD) over the substrate;

providing a first level of metal wiring being defined and embedded in a first layer of insulator over the layer of dielectric;

depositing a blanket of passivating dielectric layer (IMD) over the defined said first level of metal wiring;

patterning and etching the said passivating dielectric (IMD) to form special interlocking grid structures with open contact regions to underlying first level metal wiring;

depositing a blanket of a metal barrier layer;

patterning and defining the said metal barrier layer on top of the interlocking grid structures;

depositing a blanket of a metal layer for metal pad formation on top of the interlocking grid structures;

patterning and defining the said metal pad layer to form metal pads on interlocking grid structures;

repeating the above process stops to construct multilevel pad structures by this robust method to form metal pad contact structures for chips and IC'"'"'s.

2. The method of claim 1, wherein said substrate is a semiconductor consisting of a single crystal of silicon.

3. The method of claim 1, wherein said layers of passivating dielectric insulating material are selected from the group consisting of insulating, refractory materials, silicon oxide, silicon nitride, silicon oxynitride and polyimides.

4. The method of claim 1, wherein said layer of first level metal wiring is composed of conducting metal copper.

5. The method of claim 1, wherein the said special interlocking grid structure composed of passivating material provide improved adhesion properties to the pad metal stack consisting of the underlying metal, metal barrier layer and top metal pad layer.

6. The method of claim 1, wherein the metal barrier layer is on top of the said interlocking grid structure and is composed of tantalum nitride, with a thickness of approximately 150 Angstroms.

7. The method of claim 1, wherein said metal layer for metal pad formation, on top of the interlocking grid structures, is composed of aluminum.

8. The method of claim 1, wherein the metal pad and interlocking grid structures consist of forming a copper underlayer, forming interlocking grid structures, forming a tantalum nitride barrier layer, and forming an aluminum pad.

9. The method of claim 1, wherein the special metal pad interlocking grid structure stack is made by a robust process and has a robust interlocking structure, increasing surface roughness and area for improved adhesion properties and can be fabricated out of conducting materials for improved conductivity.

10. The method of claim 1, wherein the conducting material layers form an interlocking metal pad structure for contacts in a wide variety of applications, selected from the group consisting of chip technology, IC module technology, and solid state devices where an integrated electrical contact is necessary.

11. The method of claim 1, wherein the process steps listed in claim 1 can be repeated to form additional levels of multilevel metal pad structures.

12. A method of fabricating an integrated circuit on a substrate, using a new and improved method for fabricating aluminum metal pad structures wherein a special interlocking grid structure, for improved adhesion, is produced by this process, the method comprising the following steps:

providing a silicon substrate or IC substrate module with integrated circuits therein;

providing said substrate with a layer of dielectric, termed an interlevel dielectric (ILD) over the substrate;

providing a first level of copper conducting wiring layer being defined and embedded in a first layer of insulator, silicon oxide, over the layer of dielectric;

depositing a blanket of passivating dielectric layer (IMD) over the defined said first level of copper conducting wiring layer;

patterning and etching the said passivating dielectric (IMD) to form special interlocking grid structures with open contact regions to underlying first level of copper conducting wiring;

depositing a blanket of a metal barrier layer, comprised of a thin layer of tantalum nitride;

patterning and defining the said metal barrier layer on top of the interlocking grid structures;

depositing a blanket of an aluminum metal layer for metal pad formation on top of the interlocking grid structures;

patterning and defining the said aluminum metal pad layer to form metal pads on interlocking grid structures;

repeating the above process steps to construct multilevel pad structures by this robust method to form interlocking metal pad contact structures for chips and IC'"'"'s.

13. The method of claim 12, wherein said substrate is a semiconductor consisting of a single crystal of silicon.

14. The method of claim 12, wherein said layers of passivating dielectric insulating material are selected from the group consisting of insulating, refractory materials, silicon oxide, silicon nitride, silicon oxynitride and polyimides.

15. The method of claim 12, wherein said layer of first level metal wiring is composed of conducting metal copper.

16. The method of claim 12, wherein the said special interlocking grid structure composed of passivating material provide improved adhesion properties to the pad metal stack consisting of the underlying metal, metal barrier layer and top metal pad layer.

17. The method of claim 12, wherein the metal barrier layer is on top of the said interlocking grid structure and is composed of tantalum nitride, with a thickness of approximately 150 Angstroms.

18. The method of claim 12, wherein said metal layer for metal pad formation, on top of the interlocking grid structures, is composed of aluminum.

19. The method of claim 12, wherein the metal pad and interlocking grid structures consist of forming a copper underlayer, forming interlocking grid structures, forming a tantalum nitride barrier layer, and forming an aluminum pad.

20. The method of claim 12, wherein the special metal pad interlocking grid structure stack is made by a robust process and has a robust interlocking structure for good adhesion and conductivity, as proven by stress tests and has confirmed adhesion properties by gold wire bond pull tests, improving device, circuit reliability.

21. The method of claim 12, wherein the special metal pad interlocking grid structure stack is made by a robust process and has a robust interlocking structure, increasing surface roughness and area for improved adhesion properties and can be fabricated out of conducting materials for improved conductivity.

22. The method of claim 12, wherein the process steps listed in claim 12 can be repeated to form additional levels of multilevel metal pad structures.

23. A method of fabricating an integrated circuit on a substrate, using a unique method for fabricating aluminum metallurgy pad structure layer and lines, vias and interconnect wiring for MOSFET CMOS, memory and logic devices, and IC modules is produced by this process, the method comprising the following steps:

providing a silicon substrate or IC substrate module with integrated circuits therein;

providing said substrate with a layer of dielectric, termed an interlevel dielectric (ILD) over the substrate;

providing a first level of copper conducting wiring layer being defined and embedded in a first layer of insulator, silicon oxide, over the layer of dielectric;

depositing a blanket of passivating dielectric layer (IMD) over the defined said first level of copper conducting wiring layer;

patterning and etching the said passivating dielectric (IMD) to form special interlocking grid structures with open contact regions to underlying first level of copper conducting wiring;

depositing a blanket of a metal barrier layer, comprised of a thin layer of tantalum nitride;

patterning and defining the said metal barrier layer on top of the interlocking grid structures;

depositing a blanket of an aluminum metal layer for metal pad formation on top of the interlocking grid structures;

patterning and defining the said aluminum metal pad layer to form metal pads on interlocking grid structures;

repeating the above process steps to construct multilevel pad structures by this robust method to form reliable metal pad contact, lines and interconnect wiring structures for chips, IC'"'"'s, and IC modules, thereby using the interlocking grid for robust electrical contact or contacts, lines or interconnect wiring.

24. The method of claim 23, wherein said substrate is a semiconductor consisting of a single crystal of silicon.

25. The method of claim 23, wherein said layers of passivating dielectric insulating material are selected from the group consisting of insulating, refractory materials, silicon oxide, silicon nitride, silicon oxynitride and polyimides.

26. The method of claim 23, wherein said layer of first level metal wiring is composed of conducting metal copper.

27. The method of claim 23, wherein the said special interlocking grid structure composed of passivating material provide improved adhesion properties to the pad metal stack consisting of the underlying metal, metal barrier layer and top metal pad layer.

28. The method of claim 23, wherein the metal barrier layer is on top of the said interlocking grid structure and is composed of tantalum nitride, with a thickness of approximately 150 Angstroms.

29. The method of claim 23, wherein said metal layer for metal pad formation, on top of the interlocking grid structures, is composed of aluminum.

30. The method of claim 23, wherein the metal pad and interlocking grid structures consist of forming a copper underlayer, forming interlocking grid structures, forming a tantalum nitride barrier layer, and forming an aluminum pad.

31. The method of claim 23, wherein the special metal pad interlocking grid structure stack is made by a robust process and has a robust interlocking structure, for good adhesion and conductivity, as proven by stress tests and has confirmed adhesion properties by gold wire bond pull tests, improving device, circuit reliability.

32. The method of claim 23, wherein the special metal pad interlocking grid structure stack is made by a robust process and has a robust interlocking structure, increasing surface roughness and area for improved adhesion properties and can be fabricated out of conducting materials for improved conductivity.

33. The method of claim 23, wherein the process steps listed in claim 23 can be repeated to form additional levels of multilevel bond pads.