Method for forming graded LDD transistor using controlled polysilicon gate profile

• US 6,191,044 B1
• Filed: 10/08/1998
• Issued: 02/20/2001
• Est. Priority Date: 10/08/1998
• Status: Expired due to Fees

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Cheung, Patrick K., Steffan, Paul J., Yu, Allen S.
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Pyonin, Adam
• Application Number:
  US09/169,275
• Time in Patent Office: 866 Days
• Field of Search: 438/305, 438/713, 438/303, 438/301, 438/299, 438/595, 438/197
• US Class Current: 438/713
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

An ultra-large scale CMOS integrated circuit semiconductor device with LDD structures having reduced polysilicon gate length, reduced parasitic capacitance and gradual doping profiles is manufactured by forming a gate oxide layer over the semiconductor substrate; forming a polysilicon layer over the gate oxide layer; forming a first mask layer over the polysilicon layer; patterning and etching the first mask layer to form a first gate mask; anisotropically etching the polysilicon layer to form a polysilicon gate, wherein the polysilicon gate comprises sidewalls with re-entrant profiles, and implanting the semiconductor substrate with a dopant to penetrate portions of the sidewalls to form one or more graded shallow junctions with gradual doping profiles. The gradual doping profiles reduce parasitic capacitance and minimize hot carrier injections. Portions of the polysilicon gates with re-entrant profiles are used as mask during the ion implantation of the LDD structures to space the resultant LDD structures away from the edges of the bottom portion of the polysilicon gates. Since the LDD structures are spaced away from the edges of the polysilicon gates, the lateral diffusion of the LDD structures into the channel due to rapid thermal annealing is reduced. This results in CMOS devices with reduced parasitic capacitance.

Claims

1. A method for manufacturing an MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate dielectric layer over the semiconductor substrate;

forming a polysilicon layer over said gate dielectric layer;

forming a first mask layer over said polysilicon layer;

patterning and etching said first mask layer to form a first gate mask;

anisotropically etching said polysilicon layer using said first gate mask to form a polysilicon gate, wherein said polysilicon gate includes a gate part and a sidewall part with a re-entrant profile;

implanting the semiconductor substrate with a dopant at a first energy and a first concentration to form a shallow extension junctions in the semiconductor substrate around said polysilicon gate, said implanting also performed through said sidewall part to form said shallow extension junction with a graded doping profile under said sidewall part; and

removing the gate dielectric layer except under said gate part of said polysilicon gate.

2. The method as claimed in claim 1 wherein the step of anistropically etching said polysilicon layer includes the steps of controlling etching parameters, wherein said etching parameters include concentrations of etchants, temperature, RF power, DC bias, and magnetic field to form said re-entrant profile to control said graded doping profile.

3. The method as claimed in claim 1 wherein the step of implanting through said sidewall part forms said shallow extension junction with said graded doping profile inversely proportional to the thickness of the sidewall part above said shallow extension junction.

4. The method as claimed in claim 1 including the steps of:

annealing said semiconductor substrate after the step of implanting the semiconductor with said dopant, wherein said annealing step results in a lateral diffusion of said shallow extension junctions toward the gate part of said polysilicon gate; and

controlling said re-entrant profiles of said sidewall part, said first energy, said first concentration, or a combination thereof, so that said shallow extension junctions are formed at a distance away from said gate part of said polysilicon gate, whereby said lateral diffusion of said dopant under said gate part of said polysilicon gate is reduced.

5. The method as claimed in claim 1 including the steps of:

forming a second mask layer over said first mask layer;

patterning and etching said second mask layer using said first mask layer as an antireflective coatings to form a second gate mask prior to the step of etching said first mask layer to form said first gate mask; and

removing said first gate mask and said second gate mask prior to the step of implanting the semiconductor substrate with said dopant.

6. The method as claimed in claim 1 wherein said first mask layer is a material selected from a group consisting of oxide and nitride.

7. The method as claimed in claim 1 including:

forming a sidewall spacer under said sidewall part of said polysilicon gate;

implanting the semiconductor substrate using said polysilicon gate and said sidewall spacer as a mask using said dopant at a second energy and a second concentration to form a deep junction; and

annealing the semiconductor substrate.

8. A method for manufacturing MOS structures on a semiconductor substrate having first and second doping regions of different conductivity types, comprising the steps of:

forming a gate dielectric layer over the semiconductor substrate;

forming a polysilicon layer over said gate dielectric layer;

forming a first mask layer over said polysilicon layer

patterning and etching said first mask layer to form a first gate mask;

anisotropically etching said polysilicon layer using said first gate mask to form first and second polysilicon gates, wherein said first and second polysilicon gates each include a gate part and a sidewall part with a re-entrant profile, and wherein said first polysilicon gate is over the first doping region and the second polysilicon gate is over the second doping region;

removing said first gate mask and said second gate mask;

depositing a third mask layer over said first and second polysilicon gates and said first and second doping regions;

patterning and etching said third mask layer to expose said first polysilicon gate and said first doping region;

implanting the first doping region with a first dopant at a first energy and a first concentration to form a first shallow extension junction in the first doping region around said first polysilicon gate, said implanting also performed through said sidewall part of the first polysilicon gate to form said first shallow extension junction with a first graded doping profile under said sidewall part;

removing;

the third mask layer;

depositing a fourth mask layer over said first and second polysilicon gates and said first and second doping regions;

patterning and etching said fourth mask layer to expose said second polysilicon gate and said second doping region;

implanting said second doping region with a second dopant at a first energy and a first concentration to form a second shallow extension junction in the second doping region around said second polysilicon gate, said implanting also performed through said sidewall part of said second polysilicon gate to form said second shallow extension junction with a second graded doping profile under said sidewall part;

removing the fourth mask layer; and

removing the gate dielectric layer except under said gate parts of said first and second polysilicon gates.

9. The method as claimed in claim 8 wherein the step of anistropically etching said polysilicon layer includes the steps of controlling etching parameters, wherein said etching parameters include concentrations of etchants, temperature, RF power, DC bias, and magnetic field to form said re-entrant profile to control said graded doping profile.

10. The method as claimed in claim 8 wherein the steps of implanting through said sidewall parts form said shallow extension junctions, with said graded doping profiles inversely proportional to the thickness of the sidewall parts above said shallow extension junctions and said first and second graded doping profiles are the same.

11. The method as claimed in claim 8 including the steps of:

annealing said semiconductor substrate after the step of implanting said second dopant, wherein said annealing step results in a lateral diffusion of said first and second shallow extension junctions respectively under said first and second polysilicon gates; and

controlling said re-entrant profiles of said sidewall parts, said first energy, said first concentration, or a combination thereof, so that said shallow extension junctions are formed equally distal from said gate parts whereby said lateral diffusion under said first and second polysilicon gates is the same.

12. The method as claimed in claim 8 including:

forming first and second sidewall spacers respectively under said sidewall parts of said first and second polysilicon gates;

depositing a fifth mask layer over said first and second polysilicon gates, said first and second sidewall spacers, and said first and second doping regions;

patterning and etching said fifth mask layer to expose said first polysilicon gate, said first sidewall spacer, and said first doping region;

implanting the first doping region using said first and said sidewall spacers as a mask using said dopant at a second energy and a second concentration to form a first deep junction;

depositing a sixth mask layer over said first and second polysilicon gates, said first and second sidewall spacers, and said first and second doping regions;

patterning and etching said sixth mask layer to expose said second polysilicon gate, said second sidewall spacer, and said second doping region;

implanting the second doping region using said second polysilicon gates and said second sidewall spacer as a mask using said second dopant at a second energy and a second concentration to form a second deep junction; and

annealing the semiconductor substrate.

13. A method for manufacturing an MOS structure on a semiconductor substrate, comprising the steps of:

forming a gate oxide layer over the semiconductor substrate;

forming a polysilicon layer over said gate oxide layer;

forming a first mask layer over said polysilicon layer;

forming a second mask layer over said first mask layer;

patterning and etching said second mask layer using said first mask layer as an antireflective coating to form a second gate mask;

patterning and etching said first mask layer to form a first gate mask;

anisotropically etching said polysilicon layer using said first gate mask to form a polysilicon gate, wherein said polysilicon gate includes a gate part and a sidewall part with a re-entrant profile, said anistropically etching said polysilicon layer includes the steps of controlling etching parameters wherein said etching parameters include concentrations of etchants, temperature, RF power, DC bias, and magnetic field to form said re-entrant profile;

removing said first gate mask and said second gate mask;

implanting the semiconductor substrate with a dopant of a second conductivitiy type at a first energy and a first concentration to form a shallow extension junction around said polysilicon gate said implanting also performed through said sidewall part to form said shallow extension junction with a graded doping profile inversely proportional to the thickness of said sidewall part above said shallow extension junction; and

removing the gate oxide layer except under said gate sidewall part.

14. The method as claimed in claim 13 including the steps of:

annealing said semiconductor substrate after the step of implanting the semiconductor substrate with said dopant, wherein said annealing step results in a lateral diffusion of said shallow extension junctions toward said gate part of said polysilicon gate.

15. A method for manufacturing a PMOS structure and an NMOS structure on a semiconductor substrate having an n-type and p-type doping regions, comprising the steps of:

forming a gate dielectric layer over the semiconductor substrate;

forming a polysilicon layer over said gate dielectric layer;

forming a first mask layer over said polysilicon layer;

patterning and etching said first mask layer to form a first gate mask;

anisotropically etching said polysilicon layer using said first gate mask to form first and second polysilicon gates, wherein said first and second polysilicon gates each include a gate part and a sidewall part with a re-entrant profile, and wherein said first polysilicon gate is over the n-type doping region and the second polysilicon gate is over the p-type doping region;

depositing a third mask layer over said first and second polysilicon gates and said n-type and p-type doping regions;

patterning and etching said third mask layer to expose said first polysilicon gate and said n-type doping region;

implanting the n-type doping region with a p-type dopant at a first energy and a first concentration to form a p-type shallow extension junction in the n-type doping region around said first polysilicon gate, said implanting also performed through said sidewall part of the first polysilicon gate to form said p-type shallow extension junction with a first graded doping profile under said sidewall part;

depositing a fourth mask layer over said first and second polysilicon gates and said n-type and p-type doping regions;

patterning and etching said fourth mask layer to expose said second polysilicon gate and said p-type doping region;

implanting the p-type doping region with an n-type dopant at a first energy and a first concentration to form an n-type shallow extension junction in the p-type doping region around said second polysilicon gate, said implanting also performed through said sidewall part of said second polysilicon gate to form said n-type shallow extension junction with a second graded doping profile under said sidewall part; and

removing the gate dielectric layer except under said gate parts of said first and second polysilicon gates.

16. The method as claimed in claim 15 wherein the step of anistropically etching said polysilicon layer includes the steps of controlling etching parameters, wherein said etching parameters include concentrations of etchants, temperature, RF power, DC bias, and magnetic field to form said re-entrant profiles to control said graded doping profiles.

17. The method as claimed in claim 15 wherein the steps of implanting through said sidewall parts forms said p-type and n-type shallow extension junctions with said graded doping profiles inversely proportional to the thickness of the sidewall parts above said p-type and n-type shallow extension junctions, and said first and second graded doping profiles are the same.

18. The method as claimed in claim 15 including the steps of:

controlling said re-entrant profiles of said sidewalls parts, said first energy, said first concentration, or a combination thereof, so that said p-type and n-type shallow extension junctions are formed equally distal from said gate parts, whereby said lateral diffusion under said first and second polysilicon gates is the same; and

annealing said semiconductor substrate after the step of implanting said n-type dopant, wherein said annealing step results in a lateral diffusion of said p-type and n-type shallow extension junctions respectively under said first and second polysilicon gates.