Gain and error correction circuitry

• US 6,191,412 B1
• Filed: 05/03/2000
• Issued: 02/20/2001
• Est. Priority Date: 01/09/1998
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Afghahi, Morteza
• Primary Examiner(s): Lee, John R.
• Assistant Examiner(s): PYO, KEVIN K
• Application Number:
  US09/564,072
• Time in Patent Office: 293 Days
• Field of Search: 250/214.R, 250/214.A, 250/214.LA, 250/214.AG, 250/214.C, 250/208.1, 250/205, 327/514, 327/515, 348/296, 348/297, 348/298, 348/301, 348/308
• US Class Current: 250/214.0AG
• CPC Class Codes: G11C 27/00 Electric analogue stores, e.g. for storing instantaneous values
• CPC Class Codes: G11C 27/02 Sample-and-hold arrangements G11C27/04 takes precedence
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

Gain and error correction circuitry for metal-oxide-semiconductor (MOS) analog storage circuits, including image sensors. The correction circuitry allows the analog output signal for a storage cell to substantially track an input signal in each cell. Voltage dependent distortion and attenuation in the output signal, with respect to the input signal, is minimized, without significantly increasing the size of each cell.

Claims

1. A circuit comprising:

first portion having at least one first device receiving an input signal;

second portion having at least one second device that is a replicate of the first device, the second portion being coupled to the first portion at an intermediate node;

first control circuit for causing a first current through the second device; and

second control circuit for causing a second current through the intermediate node,

the second portion providing an output signal that is linearly proportional to the input signal in response to the first and second devices conducting the same amount of current.

2. A circuit as in claim 1 wherein the first device in the first portion is a FET configured as a source follower receiving the input signal.

3. A circuit as in claim 1 wherein the first control circuit comprises a current source and the second control circuit comprises a current sink.

4. A circuit as in claim 1 wherein the second current has a value twice the first current.

5. A method comprising:

applying an input signal to a first transistor to enable a first current through the transistor;

controlling a second current through a second transistor that is a replicate of the first transistor, the second transistor being coupled to the first transistor so that the first and second currents are summed at an intermediate node;

controlling a third current through the intermediate node, the third current being equal to twice the second current; and

reading an output signal at an output of the second transistor.

6. The method of claim 5, wherein the first and second currents are sourced into the intermediate node.

7. The method of claim 5, wherein the third current is sourced into the intermediate node.

8. The method of claim 5, wherein the input signal is a light-generated signal created by a photodetector in an image sensor array.

9. The method of claim 5 further comprising:

applying a select signal to a third transistor being stacked with the first transistor, to selectively enable the first current through the first and third transistors; and

applying a dummy signal to a fourth transistor being stacked with the second transistor, to enable the second current through the second and fourth transistors.

10. The method of claim 9, wherein the input signal is a light-generated signal created by a photodetector in an image sensor array.