Semiconductor device and memory device

• US 6,191,432 B1
• Filed: 09/02/1997
• Issued: 02/20/2001
• Est. Priority Date: 09/02/1996
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sugiyama, Naoharu, Kurobe, Atsushi
• Primary Examiner(s): CRANE, SARA W
• Application Number:
  US08/921,550
• Time in Patent Office: 1,267 Days
• Field of Search: 257/14, 257/15, 257/18, 257/19, 257/20
• US Class Current: 257/19
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A semiconductor device includes a superlattice having a first semiconductor layer having a first band-gap, a second semiconductor layer having a band-gap narrower than the first band-gap, the superlattice having a band structure with an energy level of a conduction band of the second semiconductor layer being lower than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, or a band structure with an energy level of a conduction band of the second semiconductor layer being higher than an energy level of a conduction band of the first semiconductor layer and an energy level of a valence band of the second semiconductor layer being lower than an energy level of a valence band of the first semiconductor layer, an exposed face formed on a plane different from a plane orientation on which the superlattice is formed, an end face of the superlattice being exposed to the exposed face, and a channel being formed on the exposed face.

Claims

1. A semiconductor device comprising:

a superlattice comprising a first semiconductor layer having a first band-gap, a second semiconductor layer having a band-gap narrower than said first band-gap, said superlattice having a band structure with an energy level of a conduction band of said second semiconductor layer being lower than an energy level of a conduction band of said first semiconductor layer and an energy level of a valence band of said second semiconductor layer being lower than an energy level of a valence band of said first semiconductor layer, or a band structure with an energy level of a conduction band of said second semiconductor layer being higher than an energy level of a conduction band of said first semiconductor layer and an energy level of a valence band of said second semiconductor layer being higher than an energy level of a valence band of said first semiconductor layer;

an exposed face formed on a plane different from a plane orientation on which said superlattice is formed, an end face of said superlattice being exposed to said exposed face; and

a channel selectively formed on said exposed face.

2. A semiconductor device according to claim 1, composing a first field effect transistor having a channel storing electrons in a lower one of conduction band energy potentials of said first semiconductor layer and said second semiconductor layer forming said super-lattice, and a second field effect transistor having a channel storing holes in a lower one of valence band energy potentials of said first semiconductor layer and said second semiconductor layer forming said superlattice.

3. A semiconductor device according to claim 2, wherein said first semiconductor layer comprises silicon, or an alloy crystal of silicon and germanium, and said second semiconductor layer comprises an alloy crystal of silicon and germanium having a higher germanium content ratio as compared with said first semiconductor layer, or germanium.

4. A semiconductor device according to claim 3, wherein said first semiconductor layer comprises silicon, or an alloy crystal of silicon and germanium, said silicon or an alloy crystal of silicon and germanium containing a tensile strain, and said second semiconductor layer comprises an alloy crystal of silicon and germanium having a higher germanium content ratio as compared with said first semiconductor layer, or germanium, said alloy crystal of silicon and germanium, or germanium containing a compressive strain.

5. A semiconductor device according to claim 1, further comprising a first electrode disposed on one end of said channel of said exposed face, and a second electrode disposed on the other end of said channel of said exposed face.

6. A semiconductor device comprising:

a semiconductor substrate having a quantum well layer exposed annularly; and

a first electrode disposed to be insulated from said quantum well layer,

wherein when a voltage is applied to said first electrode, a conduction channel region which becomes a quantum well having a small width is formed on the exposed face of said quantum well layer exposed annularly.

7. A semiconductor device according to claim 6, wherein said semiconductor substrate has a trench, and consequently said quantum well layer is exposed annularly.

8. A semiconductor device according to claim 7, further comprising a second electrode connected to one end of said conduction channel region, and a third electrode connected to the other end of said conduction channel region.

9. A semiconductor device according to claim 8, wherein said semiconductor substrate has a plurality of trenches and a plurality of first electrodes associated with said trenches, a conduction channel region is formed in each of said plurality of trenches, and a second electrode connected to one end of said conduction channel region and a third electrode connected to the other end of said conduction channel region are formed;

said third electrode of arbitrary one of said plurality of trenches and said second electrode of an adjacent trench are connected together by conductor wiring; and

when a voltage is applied to said plurality of first electrodes, said plurality of conduction channel regions are connected in series via said third electrode, said conductor wiring, and said second electrode to form inductance.

10. A semiconductor device according to claim 6, wherein said semiconductor substrate has a columnar projection, and consequently said quantum well layer is exposed annularly.

11. A semiconductor device comprising:

a semiconductor substrate having at least one island-shaped region and a trench, a quantum well layer being exposed annularly on all side faces of said trench; and

an electrode formed within said trench, said electrode being disposed to be insulated from said semiconductor substrate having at least one island region,

wherein when a voltage is applied to said electrode, a conduction channel region which becomes a quantum well having a small width is formed on the exposed face of said quantum well layer exposed annularly.

12. A semiconductor device comprising:

a semiconductor projection formed on a semiconductor substrate, said semiconductor projection having a quantum well layer inside;

a first electrode formed on a side face of said semiconductor projection to be insulated from said side face of said semiconductor projection;

at least one trench formed on an upper face of said semiconductor projection so as to expose said quantum well layer annularly; and

a second electrode formed in said trench to be insulated from said semiconductor projection,

wherein when a voltage is applied to said first electrode or said second electrode, an annular conduction channel region which becomes a quantum well having a small width is formed on an face of said quantum well layer opposed to an electrode subjected to voltage application and included in said first electrode and said second electrode.