Mini flash process and circuit

• US 6,191,444 B1
• Filed: 09/03/1998
• Issued: 02/20/2001
• Est. Priority Date: 09/03/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Green, James E., Clampitt, Darwin A.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US09/146,298
• Time in Patent Office: 901 Days
• Field of Search: 257/288, 257/314, 257/315, 257/324, 257/326, 257/368, 438/241
• US Class Current: 257/315
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method for making reduced-size FLASH EEPROM memory circuits, and to the resulting memory circuit. An FET integrated circuit having two different gate oxide thicknesses deposited at a single step, where a portion of the thickness of the thicker oxide is formed, that oxide is removed from the area of the chip to have the thinner oxide, then the rest of the thicker oxide is grown during the time that the thinner oxide is grown on the area of the chip to have the thinner oxide. Layers for the floating gate stacks are deposited. Trenches are etched in a first, and then a second perpendicular direction, and the perpendicular sides of the stacks are covered with vertical-plane nitride layers in two separate operations. Tungsten word lines and bit contacts are deposited. Aluminum-copper lines are deposited on the bit lines.

Claims

1. An electronic circuit comprising:

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric of a second thickness thinner than the first thickness; and

a third set of one or more transistors each having a gate dielectric of a third thickness thinner than the second thickness, wherein the gate dielectric of the second set of transistors is grown as part of a dielectric growth process that adds thickness to the gate dielectric of the first set of transistors, and the gate dielectric of the third set of transistors is grown as part of a dielectric growth process that adds thickness both to the gate dielectric of the first set of transistors and to the gate dielectric of the second set of transistors.

2. The circuit according to claim 1, wherein an initial thickness of dielectric is grown on both a first chip area for the first set of transistors and a second chip area for the second set of transistors and a third chip area for the third set of transistors, and is substantially removed from the second chip area and the third chip area, and is substantially not removed from the first chip area, and a first intermediate thickness of dielectric is grown on the first chip area and a second intermediate gate thickness is grown on the second and third chip areas and is substantially removed from the third chip area, and is substantially not removed from the first chip area and the second chip area, and a first, second and third final thickness of dielectric is grown on the first, second and third chip areas, respectively.

3. The circuit according to claim 2, wherein the first, second, and third chip areas are substantially co-planar.

4. An electronic circuit comprising:

a first set of one or more transistors each having a gate dielectric layer of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness different than the first thickness; and

a third set of one or more transistors each having a gate dielectric of a third thickness thinner than the second thickness, wherein the gates having the second thickness are grown as part of a dielectric growth process that adds thickness to gates having the first thickness, and gates having the third thickness are grown as part of a dielectric growth process that adds thickness both to the gates having the first thickness and to gates having the second thickness,

wherein the first thickness is thicker than the second thickness, and wherein an initial thickness of dielectric is grown on both a first chip area for the first set of transistors and a second chip area for the second set of transistors, and is substantially removed from the second chip area, and is substantially not removed from the first chip area, and a first and second final thickness of dielectric is grown on the first and second chip areas, respectively, and

wherein the gate dielectric of the third thickness is an oxide layer sufficiently thin to allow Fowler-Nordheim tunneling for programming or erasing, formed after at least portions of the first thickness and the second thickness and is covered by a polysilicon floating gate, a polysilicon control gate, and a dielectric layer separating the polysilicon floating gate and the polysilicon control gate.

5. The circuit according claim 4, wherein the gate dielectric of the first thickness is a gate oxide sufficiently thick to prevent electrical breakdown at operating voltages, and is covered by a polysilicon transistor gate that was deposited during the step that deposited the polysilicon floating gate.

6. The circuit according to claim 4, wherein at least a portion of the gate dielectric of the second set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

7. The circuit according to claim 4, wherein at least a portion of the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

8. An electronic circuit comprising:

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric of a second thickness thinner than the first thickness; and

a third set of one or more transistors each having a gate dielectric layer;

a floating-gate poly layer over the dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

a nitride layer covering the source end from the inter-poly nitride layer to the substrate, wherein the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the second set of transistors.

9. The circuit according claim 8, further comprising:

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end; and

a tungsten gate contact formed to substantially contact the WSix layer.

10. The circuit according claim 9, further comprising:

an aluminum-copper (AlCu) line formed substantially in contact with the tungsten drain contact.

11. An electronic circuit comprising:

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric of a second thickness thinner than the first thickness; and

a third set of one or more transistors each having;

a third gate dielectric layer;

a floating-gate poly layer over the dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer; and

a tungsten-silicide (WSix) layer over the control-gate poly layer,

wherein the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the second set of transistors.

12. The circuit according to claim 11, wherein at least a portion of the gate dielectric of the second set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

13. The circuit according to claim 11, wherein at least a portion of the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

14. An electronic circuit comprising:

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric of a second thickness thinner than the first thickness; and

a third set of one or more transistors each having;

a third gate dielectric layer;

a floating-gate poly layer over the dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer;

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end; and

a tungsten gate contact formed to substantially contact the WSix layer

wherein the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the second set of transistors.

15. The circuit according to claim 14, wherein at least a portion of the gate dielectric of the second set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

16. The circuit according to claim 14, wherein at least a portion of the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

17. A FLASH memory chip comprising:

a first set of one or more transistors each having a gate dielectric layer of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness different than the first thickness, wherein the first thickness is thicker than the second thickness;

a third set of one or more transistors each having a gate dielectric of a third thickness thinner than the second thickness, wherein the gate dielectric of the second set of transistors is grown as part of a dielectric growth process that adds thickness to the gate dielectric of the first set of transistors, and the gate dielectric of the third set of transistors is grown as part of a dielectric growth process that adds thickness both to the gate dielectric of the first set of transistors and to the gate dielectric of the second set of transistors, wherein the third set of transistors are used as electrically erasable and programmable read only memory (EEPROM) storage cells and also include;

a floating-gate poly layer over the second dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

18. The FLASH memory chip according claim 17, further comprising:

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end; and

a tungsten gate contact formed to substantially contact the WSix layer.

19. The FLASH memory chip according claim 18, further comprising:

an aluminum-copper (AlCu) line formed substantially in contact with the tungsten drain contact.

20. A FLASH memory chip comprising:

a first set of one or more transistors each having a gate dielectric layer of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness different than the first thickness, wherein the first thickness is thicker than the second thickness;

a third set of one or more transistors each having a gate dielectric of a third thickness thinner than the second thickness, wherein the gate dielectric of the second set of transistors is grown as part of a dielectric growth process that adds thickness to the gate dielectric of the first set of transistors, and the gate dielectric of the third set of transistors is grown as part of a dielectric growth process that adds thickness both to the gate dielectric of the first set of transistors and to the gate dielectric of the second set of transistors, wherein the third set of transistors are used as electrically erasable and programmable read only memory (EEPROM) storage cells and also include;

a floating-gate poly layer over the second dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer; and

a tungsten-silicide (WSix) layer over the control-gate poly layer.

21. A FLASH memory chip comprising:

a first set of one or more transistors each having a gate dielectric layer of a first thickness;

a second set of one or more transistors each having a gate dielectric layer of a second thickness different than the first thickness, wherein the first thickness is thicker than the second thickness;

a third set of one or more transistors each having a gate dielectric of a third thickness thinner than the second thickness, wherein the gate dielectric of the second set of transistors is grown as part of a dielectric growth process that adds thickness to the gate dielectric of the first set of transistors, and the gate dielectric of the third set of transistors is grown as part of a dielectric growth process that adds thickness both to the gate dielectric of the first set of transistors and to the gate dielectric of the second set of transistors, wherein the third set wherein the second set of transistors are used as electrically erasable and programmable read only memory (EEPROM) storage cells and also include;

a floating-gate poly layer over the second dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer;

a tungsten drain contact formed substantially adjacent to the nitride layer covering the drain end;

a tungsten source contact formed substantially adjacent to the nitride layer covering the source end; and

a tungsten gate contact formed to substantially contact the WSix layer.

22. A FLASH memory chip comprising:

a first set of one or more transistors each having a gate dielectric of a first thickness, the first set of transistors used as electrically erasable and programmable read only memory (EEPROM) storage cells; and

a second set of one or more transistors each having a gate dielectric of a second thickness thicker than the first thickness, the second set of transistors used as logic and amplifier circuits, wherein the gate dielectric of the first set of transistors is grown as part of a dielectric growth process that adds thickness to the gate dielectric of the second set of transistors.

23. The FLASH memory chip according to claim 22, wherein an initial thickness of dielectric is grown on both a first chip area for the first set of transistors and a second chip area for the second set of transistors, and is removed from only the second chip area, and a first and second final thickness of dielectric is grown on the first and second chip areas, respectively.

24. The FLASH memory chip according to claim 23, wherein the first and second chip areas are substantially co-planar.

25. The FLASH memory chip according to claim 24, further comprising:

a floating-gate poly layer over the second dielectric layer;

an inter-poly nitride layer over the floating-gate poly layer;

a control-gate poly layer over the inter-poly nitride layer;

a tungsten-silicide (WSix) layer over the control-gate poly layer, wherein the gate dielectric layer, the floating-gate poly layer, the inter-poly nitride layer, the control-gate poly layer, and the tungsten-silicide (WSix) layer form a floating-gate stack on a silicon substrate, the stack having a first side that extends into a first trench and a second side that extends into a second trench into the silicon substrate, and a drain end and a source end;

a nitride layer covering the first side of the stack from the inter-poly nitride layer to the first trench;

a nitride layer covering the second side of the stack from the inter-poly nitride layer to the second trench;

a nitride layer covering the drain end from the inter-poly nitride layer to the substrate; and

a nitride layer covering the source end from the inter-poly nitride layer to the substrate.

26. An electronic circuit comprising:

a first set of one or more transistors each having a gate dielectric of a first thickness;

a second set of one or more transistors each having a gate dielectric of a second thickness that is thinner than the first thickness; and

a third set of one or more transistors each having a gate dielectric of a third thickness that is thinner than the second thickness, wherein the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the second set of transistors.

27. The circuit according to claim 26, wherein at least a portion of the gate dielectric of the second set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

28. The circuit according to claim 27, wherein at least a portion of the gate dielectric of the third set of transistors is formed in a later processing step than a processing step used to form at least some of the gate dielectric of the first set of transistors.

29. The circuit according to claim 26, wherein an initial thickness of dielectric is grown on both a first chip area for the first set of transistors and a second chip area for the second set of transistors and a third chip area for the third set of transistors, and is substantially removed from the second chip area and the third chip area, and is substantially not removed from the first chip area, and a first intermediate thickness of dielectric is grown on the first chip area and a second intermediate gate thickness is grown on the second and third chip areas and is substantially removed from the third chip area, and is substantially not removed from the first chip area and the second chip area, and a first, second and third final thickness of dielectric is grown on the first, second and third chip areas, respectively.

30. The circuit according to claim 26, wherein one surface of the gate dielectric of the first third set of transistors is substantially co-planar to one surface of the gate dielectric of the second and to one surface of the gate dielectric of the third set of transistors.