Electrically programmable memory cell array, using charge carrier traps and insulation trenches

• US 6,191,459 B1
• Filed: 01/08/1997
• Issued: 02/20/2001
• Est. Priority Date: 01/08/1996
• Status: Expired due to Term

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Willer, Josef, Hofmann, Franz, Reisinger, Hans, Krautschneider, Wolfgang
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Weiss, Howard
• Application Number:
  US08/780,488
• Time in Patent Office: 1,504 Days
• Field of Search: 257/330, 257/331, 257/390, 438/259, 438/270
• US Class Current: 257/390
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electrically programmable memory cell array is formed of memory cells, which include a vertical MOS transistor. The MOS transistor has a gate dielectric of a material with charge carrier traps. The memory cells are disposed along opposite edges of striplike, parallel insulation trenches. The width and spacing of the insulation trenches are preferably identical. The space required per memory cell of the memory cell array is 2F², where F is the minimum structural size in the technology employed. The memory cells are programmed by selectively injecting electrons into the gate dielectric.

Claims

1. An electrically programmable memory cell array, comprising:

a semiconductor substrate having a main face, and a cell field with a plurality of memory cells disposed on said main face of said semiconductor substrate, said semiconductor substrate being doped, at least in a region of said cell field, with a first conductivity type, said cell field having a plurality of substantially parallel strip-shaped insulation trenches formed therein, said insulation trenches each having a bottom, said cell field having a length extending entirely across said cell field;

strip-shaped doped zones disposed between adjacent said insulation trenches on said main face, and on said bottom of said insulation trenches, said doped zones disposed on said bottom of said insulation trenches being disposed within said insulation trenches, said doped zones being doped with a second conductivity type, opposite said first conductivity type, and extending substantially parallel to said insulation trenches, said doped zones extending entirely across said length of said cell field;

said insulation trenches being filled with insulating material forming a planar surface on said main face of said semiconductor substrate;

each of said memory cells being disposed on mutually opposite edges of said insulation trenches;

said memory cells including at least one MOS transistor having a gate electrode disposed vertically relative to said main face, said MOS transistor having a gate dielectric formed of a material with charge carrier traps;

word lines extending transversely to said insulation trenches, each of said word lines connected to said gate electrode of a respective said vertical MOS transistor disposed below a respective said word line;

each of said memory cells formed with a hole extending from one edge of one of said insulation trenches inward into said insulation trench, whose surface being provided with said gate dielectric, said hole being filled with said gate electrode such that said strip-shaped doped zones adjoining the edge form source/drain zones of said vertical MOS transistor; and

said doped zones disposed on said main face and on said bottom of said insulation trenches connecting respective source/drain zones of said vertical transistors disposed adjacent to one another along an edge of a respective one of said insulation trenches.

2. The memory cell array according to claim 1, wherein a spacing between mutually adjacent insulation trenches is substantially equal to a width of said insulation trenches;

and each two said memory cells disposed on opposite edges of a respective insulation trench share one common hole extending over an entire width of said insulation trench.

3. The memory cell array according to claim 1, wherein said gate dielectric of said MOS transistor comprises a dielectric multiple layer with at least a first layer and a second layer, said first layer having an increased charge carrier trapping cross section relative to said second layer.

4. The memory cell array according to claim 3, wherein said first layer with the increased charge carrier trapping cross section includes one or more materials selected from the group consisting of Si₃N₄, Ta₂O₅, Al₂O₃ and TiO₂;

and said second layer includes one or more materials selected from the group consisting of SiO₂, Si₃N₄ or Al₂O₃.

5. The memory cell array according to claim 1, wherein said gate dielectric of said MOS transistors includes a dielectric layer having foreign atoms incorporated therein, said foreign atoms having an increased charge carrier trapping cross section relative to said dielectric layer.

6. The memory cell array according to claim 5, wherein said dielectric layer is an SiO₂ layer;

and said foreign atoms include at least one element selected from the group consisting of W, Pt, Cr, Ni, Pd, Si and Ir.