Test circuit for an AFCI/GFCI circuit breaker

• US 6,191,589 B1
• Filed: 03/29/1999
• Issued: 02/20/2001
• Est. Priority Date: 03/29/1999
• Status: Expired due to Fees

• Current Assignee: GSK Technologies Incorporated
• Original Assignee: George A. Spencer
• Inventors: Clunn, Robert Henry
• Primary Examiner(s): Metjahic, Safet
• Assistant Examiner(s): Deb, Anjan K
• Application Number:
  US09/277,879
• Time in Patent Office: 694 Days
• Field of Search: 324/424, 324/127, 324/158.1, 361/42, 703/18
• US Class Current: 324/424
• CPC Class Codes: G01R 15/183 using transformers with a magnetic core
• CPC Class Codes: G01R 31/3274 Details related to measuring, e.g. sensing, displaying or computing; Measuring of variables related to the contact pieces, e.g. wear, position or resistance measuring contact resistance G01R27/205
• CPC Class Codes: H02H 1/0007 concerning the detecting means in general G01R or other subclasses of G01; reed switches H01H71/2445
• CPC Class Codes: H02H 1/0038 concerning the connection of the detecting means, e.g. for reducing their number
• CPC Class Codes: H02H 3/334 with means to produce an artificial unbalance for other protection or monitoring reasons or remote control H02H3/338 takes precedence

Abstract

A novel toroidal core current sensor for an AFCI/GFCI Circuit Breaker and a test circuit configuration based thereon is disclosed. The current sensor has a plurality of load current conductors extending therethrough. One of the conductors carrying a load current has a portion of the load current shunted outside the core through a shunt conductor which is connected in parallel with one of the load current conductors. The secondary of the transformer outputs a current value proportional to and substantially less than the load current which may be, for example, detected by a control circuit which compares the current value against predetermined stored criteria and operates a circuit breaker accordingly. In the test circuit a power source and a waveform generator are provided for operating an AFCI\GFCI circuit breaker having the shunted current sensor and injecting test signals into a terminal of the circuit breaker. The unique properties of the shunted current sensor permit a wide range of fault conditions to be applied at low signal power because of the relatively high sensitivity the shunted current sensor provides to the AFCI\GFCI circuit breaker.

Claims

1. A test circuit for testing a circuit breaker, comprising:

a circuit breaker, including;

at least first and second conductors for carrying load current between a source and a load, and having at least one series breaking element for interrupting the flow of said load current,

at least a first current sensor having an output coupled to said circuit breaker, wherein said at least first and second conductors are coupled to said current sensor for sensing the net current of said load current carried on said at least first and second conductors,

wherein said current sensor further includes a shunt connected at each end to said first conductor for bypassing a small portion of said load current around said current sensor to unbalance the net flux producing an output of said current sensor, thereby increasing the detection sensitivity of said current sensor to a test current coupled in series with one of said first and second conductors, and

a control circuit for detecting said test current, and providing an indication responsive to said test current; and

a waveform generator circuit connected to said one of said first and second conductors for injecting a waveform including said test current into one of said conductors during a test operation wherein the other of said first and second mains conductors is open circuited.

2. The test circuit of claim 1, wherein said circuit breaker comprises both arc fault and ground fault detection circuitry.

3. The test circuit of claim 1, wherein said waveform includes both a bit pattern and a test current for testing said arc fault detection circuitry output from said waveform generator circuitry, and wherein said test current is a smaller replica of a load current arc fault.

4. The test circuit of claim 3, wherein said bit pattern instructs said control circuit to disable said ground fault detection circuitry of said circuit breaker during testing of said arc fault detection circuitry.

5. The test circuit of claim 3, wherein said waveform is of a low voltage and current which is injected into one of said at least first and second conductors during said test operation.

6. The test circuit of claim 5, wherein said waveform is injected into a neutral conductor.

7. The test circuit of claim 1, wherein said control circuit processes said test current by comparing said test current with predetermined limits, and provides an indication responsive to said test current being outside said predetermined limits.

8. The test circuit of claim 1, wherein said current sensor is a toroid core transformer wherein said first and second conductors pass through said toroid core.

9. The test circuit of claim 1, wherein said first current sensor is a coreless transformer having N turns.

10. The test circuit of claim 1, wherein said first current sensor has only said third conductor extending therethrough.

11. The test circuit of claim 10, wherein said first current sensor is a toroid core transformer.

12. The test circuit of claim 1, wherein said first current sensor is a coreless transformer having N turns.

13. A method of testing a circuit breaker, comprising the steps of:

providing a circuit breaker coupled to at least first and second conductors for carrying load current between a source and a load, and having at least one series breaking element for interrupting the flow of current to the load;

providing at least a first current sensor having an output coupled to the circuit breaker, the at least first and second conductors being coupled to the first current sensor for sensing the net current carried on the at least first and second conductors;

including in the first current sensor a shunt connected at each end to the first conductor for bypassing a small portion of the load current around the first current sensor to unbalance the net flux producing an output of the current sensor, thereby increasing the detection sensitivity of the current sensor to a test current coupled in series with one of the first and second conductors;

injecting from a waveform generator connected to the one of the first and second conductors a waveform including a test current into one of the first and second conductors during a test operation wherein the other of the one of the first and second mains conductors is open circuited;

detecting the test current with a control circuit; and

providing an indication responsive to the test current.

14. The method of claim 13, wherein the step of providing a circuit breaker comprises the step of:

providing a circuit breaker having both arc fault detection and ground fault detection circuitry.

15. The method of claim 13, wherein the step of injecting comprises the step of:

outputting from the waveform generator both a bit pattern and a test current for testing the arc fault detection circuitry, and wherein the test current is a smaller replica of a load current arc fault.

16. The method of claim 15, wherein the step of outputting comprises the step of:

disabling the ground fault detection circuitry responsive to the bit pattern, of the circuit breaker during testing of the arc fault detection circuitry.

17. The method of claim 13, wherein the step of injecting comprises the step of:

injecting a test current into one of the first and second conductors which test current has a voltage and current which is substantially less than the load voltage and current during normal operation.

18. The method of claim 17, wherein the step of injecting comprises the step of:

injecting the test current into a neutral conductor.

19. The method of claim 13, wherein the step of providing an indication comprises the steps of:

comparing the test current detected in the step of detecting with predetermined limits; and

tripping the breaking elements in response to the test current being outside the predetermined limits.

20. The method of claim 13, wherein the step of providing at least a first current sensor comprises the step of:

providing a toroid core transformer wherein the first and second conductors pass through the toroid core.

21. The method of claim 13, wherein the step of:

providing at least a first current sensor comprises the step of providing a coreless transformer having a secondary winding having N turns.

22. The method of claim 13, wherein the step of:

providing at least a first current sensor comprises the step of providing only the shunt extending therethrough.

23. The method of claim 22, wherein the step of:

providing at least a first current sensor comprises the step of providing a toroid core transformer.

24. The method of claim 22, wherein the step of:

providing at least a first current sensor comprises the step of providing a coreless transformer having a secondary winding having N turns.

25. A test circuit for testing a circuit breaker, comprising:

a circuit breaker under test, said circuit breaker including;

first and second mains conductors coupleable to a power line;

a control circuit for operating the circuit breaker in the presence of a fault current in said mains conductors;

wherein

said control circuit is operatively responsive to a shunted current sensor coupled to said mains conductors wherein a shunt portion of said shunted current sensor is coupled at each end to a select one of said mains conductors and bypasses only a small fraction of current flowing in said select one of said mains conductors;

a waveform generator for injecting a test signal in series with one of said mains conductors wherein said test signal includes a smaller replica of an expected actual fault current; and

a power source for supplying operating voltages to said circuit breaker.

26. The circuit of claim 25, wherein said circuit breaker comprises:

separable contacts in at least one of said first and second mains conductors; and

an indicator operatively responsive to the presence of said fault current.

27. The circuit of claim 25, wherein said shunted current sensor comprises:

a transformer having a toroid core and an output from a secondary winding thereof coupled to an input to said control circuit wherein said first and second mains conductors pass through said toroid core; and

a shunt conductor connected at each end to one of said mains conductors for unbalancing the net flux in said toroid core.

28. The circuit of claim 25, wherein said waveform generator comprises:

a source of said test signal providing reduced amplitude replicas of current waveforms representing full load arcing events; and

an amplifier for receiving said test signal from said source and coupling said test signal to said one of said mains conductors.

29. The circuit of claim 25, wherein said waveform generator comprises:

a source of a coded signal having embedded therein a command instruction; and

a coupling circuit for including said coded signal with said test signal.

30. The circuit of claim 29, wherein said command instruction comprises:

information for preconfiguring said control circuit to disable a ground fault sensing circuit therein during a period when said test signal is injected into one of said mains conductors.

31. A circuit for testing an electronic circuit breaker having line and neutral conductors coupleable in series with the line and neutral conductors of a power line and having a control circuit for operating separable contacts in at least one of said line and neutral conductors, comprising:

a differential sensor responsive to currents flowing in said line and neutral conductors and having an output coupled to an input of said control circuit in said circuit breaker;

a power source coupled to said circuit breaker for providing operating voltages thereto; and

a waveform interface circuit for coupling one or more test waveforms from a source external to said circuit breaker to one of said line and neutral conductors wherein a portion of a first one of said test waveforms coupled by said interface circuit includes a coded signal for preconfiguring said circuit breaker for testing.

32. The apparatus of claim 31, wherein said differential current sensor comprises:

a transformer located within said circuit breaker and having a toroid core and an output from a secondary winding thereof coupled to said input of said control circuit, wherein said line and neutral conductors pass through said toroid core.

33. The apparatus of claim 31, said electronic circuit breaker comprising:

line and neutral conductors;

a housing containing said separable contacts, said control circuit and said differential sensor; and

connection means for coupling said line and neutral conductors of said power line to said line and neutral conductors respectively of said circuit breaker.

34. The apparatus of claim 31, wherein said waveform interface comprises:

a source of said test waveforms providing reduced amplitude replicas of current waveforms representing full load arcing events; and

an amplifier for receiving said test waveform from said source and coupling said waveforms to said one of said line and neutral conductors.

35. The apparatus of claim 31, wherein said test waveforms are coupled to said neutral conductor.

36. The apparatus of claim 31, wherein said neutral conductor provides a summing point for a plurality of waveform interface circuits.

37. The apparatus of claim 35, wherein said plurality of waveform interface circuits each couple a component of a composite test waveform to said neutral conductor.

38. The apparatus of claim 31, wherein said waveform interface circuit provides a summing point for a plurality of components of a composite test waveform.

39. The apparatus of claim 31, wherein said coded signal comprises:

a coded sequence of waveform transitions; and

a command instruction embedded in said coded sequence.

40. The apparatus of claim 38, wherein said coded sequence comprises:

a binary output pattern having a substantially minimum offset value.

41. The apparatus of claim 38, wherein said command instruction comprises:

a signal for disabling a ground fault detection function in said circuit breaker for a predetermined interval while a test waveform is coupled by said waveform interface.

42. The apparatus of claim 31, wherein said test waveforms comprise:

selectable, reduced amplitude replicas of current waveforms representing actual arcing events.