Programmable oscillator scheme

• US 6,191,660 B1
• Filed: 03/24/1999
• Issued: 02/20/2001
• Est. Priority Date: 03/24/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren A., Mar, Monte F.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/275,336
• Time in Patent Office: 699 Days
• Field of Search: 331/57, 331/111, 331/177.R, 331/177.V, 331/176
• US Class Current: 331/111
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply

Abstract

A circuit including an oscillator circuit, a current generator circuit and a voltage generator circuit. The oscillator circuit may be configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal. The current generator may be configured to generate said first control signal in response to a first adjustment signal. The voltage generator circuit may be configured to generate the second control signal in response to a second adjustment signal.

Claims

1. A circuit comprising:

an oscillator circuit configured to generate an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal;

a current generator configured to generate said first control signal in response to a first adjustment signal received from a digital-to-analog converter;

a trim circuit configured to generate a second adjustment control signal; and

a band gap voltage generator circuit configured to generate said second control signal in response to said second adjustment signal.

2. The circuit according to claim 1, wherein said first adjustment signal is generated from said digital-to-analog converter.

3. The circuit according to claim 1, wherein said trim circuit comprises a memory element selected from the group consisting of flash EEPROM, EPROM, RAM, ROM, and other programmable elements.

4. The circuit according to claim 1, wherein said voltage generator comprises a band gap voltage generator.

5. The circuit according to claim 1, wherein said first and second control signals are generated in further response to a feedback of said output signal.

6. The circuit according to claim 5, wherein said feedback is generated in further response to one or more capacitors and one or more transistors.

7. The circuit according to claim 5, wherein said feedback is generated in response to:

a first transistor and a first capacitor configured to generate a positive transition of said feedback signal; and

a second transistor and a second capacitor configured to generate the negative transition of the feedback signal.

8. The circuit according to claim 1, wherein said oscillator comprises a current controlled oscillator.

9. The circuit according to claim 3, wherein said trim circuit adjusts said second adjustment signal in response to said programmable elements.

10. The circuit according to claim 1, wherein said current generator compensates for temperature variations in the frequency of said output signal.

11. The circuit according to claim 1, wherein said output signal comprises a differential output signal.

16. The circuit according to claim 10, wherein said current generator is further configured to charge one or more capacitors to a controlled voltage generated by said band gap voltage generator.

17. The circuit according to claim 1, wherein said trim circuit is further configured to generate a third adjustment signal and said first control signal is further generated in response to said third adjustment signal.

18. The circuit according to claim 1, wherein said band gap voltage generator is further configured to generate a fourth adjustment signal and said first control signal is further generated in response to said fourth adjustment signal.

12. A circuit comprising:

means for generating an output signal having a frequency in response to (i) a first control signal and (ii) a second control signal;

means for generating said first control signal from a current generator in response to a first adjustment signal received from a digital-to-analog converter;

means for generating a second adjustment signal; and

means for generating said second control signal from a band gap voltage generator circuit in response to said second adjustment signal.

13. A method for programming the frequency of an output signal comprising the steps of:

(a) generating said output signal having said frequency in response to (i) a first control signal and (ii) a second control signal;

(b) generating said first control signal from a current generator in response to a first adjustment signal received from a digital-to-analog converter;

(c) generating a second adjustment signal; and

(d) generating said second control signal in response to said second adjustment signal.

14. The method according to claim 13 further comprising the step of:

generating said first and second control signals coupled to a feedback of said output signal.

15. The method according to claim 13, wherein said output signal comprises a differential output signal.