Efficient two-stage digital-to-analog converter using sample-and-hold circuits

• US 6,191,720 B1
• Filed: 12/30/1998
• Issued: 02/20/2001
• Est. Priority Date: 12/30/1998
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zhang, Ligang
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): JeanPierre, Peguy Jean
• Application Number:
  US09/223,042
• Time in Patent Office: 783 Days
• Field of Search: 341/154, 341/145, 341/144, 341/155, 341/122, 341/141
• US Class Current: 341/145
• CPC Class Codes: H03M 1/682 both converters being of the unary decoded type
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals

Abstract

The present invention is a method and apparatus for converting a digital word into an analog quantity. A first plurality of signals is generated from a resistor network. A first signal is selected from the first plurality of signals based on a first half of the digital word. A second plurality of signals is generated from the resistor network using the selected first signal. A second signal is selected from the second plurality of signals based on a second half of the digital word. The second signal corresponds to the analog quantity.

Claims

1. A method for converting a digital word into an analog quantity, the method comprising:

(a) generating a first plurality of signals from a resistor network;

(b) selecting a first signal from the first plurality of signals based on a first half of the digital word;

(c) generating a second plurality of signals from the single resistor network using the selected first signal; and

(d) selecting a second signal from the second plurality of signals based on a second half of the digital word, the second signal corresponding to the analog quantity.

2. The method of claim 1 wherein selecting a first signal comprises:

(b1) decoding the first half of the digital word to generate a first control word to a switching array, the switching array transferring the first plurality of signals according to the first control word; and

(b2) combining the transferred first plurality of signals to generate the first signal.

3. The method of claim 1 wherein generating a second plurality of signals comprises:

(c1) sampling the selected first signal in a first clock period;

(c2) holding the sampled first signal in a second clock period; and

(c3) providing the sampled and held first signal to the resistor network.

4. The method of claim 1 wherein selecting a second signal comprises:

(d1) decoding the second half of the digital word to generate a second control word to a switching array, the switching array transferring the second plurality of signals according to the second control word; and

(d2) combining the transferred second plurality of signals to generate the second signal.

5. A method for converting a digital word into an analog quantity, the method comprising:

(a) generating a first plurality of signals from a resistor network;

(b) selecting first top and bottom signals from the first plurality of signals based on a first half of the digital word;

(c) generating a second plurality of signals from the resistor network using the selected first top and bottom signals; and

(d) selecting second top and bottom signals from the second plurality of signals based on a second half of the digital word, one of the second top and bottom signals corresponding to the analog quantity.

6. The method of claim 5 wherein selecting first top and bottom signals comprises:

(b1) decoding the first half of the digital word to generate a first control word to a switching array, the switching array transferring the plurality of signals according to the first control word; and

(b2) combining the transferred signals to generate the first top and bottom signals.

7. The method of claim 5 wherein generating a second plurality of signals comprises:

(c1) sampling the selected first top and bottom signals in a first clock period;

(c2) holding the sampled first top and bottom signals in a second clock period; and

(c3) providing the sampled and held first top and bottom signals to the resistor network.

8. The method of claim 7 further comprising:

coupling the sampled and held first top and bottom signals to top and bottom drive circuits based on a select signal in the second clock period to generate top and bottom feedback signals; and

coupling the top and bottom feedback signals to the resistor network to generate the second plurality of signals.

9. The method of claim 8 wherein coupling the sampled and held first top and bottom signals comprises:

coupling the sampled and held first top and bottom signals to the top and bottom drive circuits, respectively, when the select signal is at a first logic level; and

coupling the sampled and held first top and bottom signals to the bottom and top drive circuits, respectively, when the select signal is at a second logic level.

10. The method of claim 5 wherein selecting second top and bottom signals comprises:

(d1) decoding the second half of the digital word to generate a second control word to a switching array, the switching array transferring the second plurality of signals according to the second control word; and

(d2) combining the transferred second plurality of signals to generate the second top and bottom signals.

11. An apparatus to convert a digital word to an analog quantity, the apparatus comprising:

a single resistor network to generate a first plurality of signals;

an input multiplexer coupled to receive the digital word to provide a first half and a second half of the digital word;

a selector coupled to the resistor network to select a first signal from the first plurality of signals based on the first half of the digital word;

a sample-and-hold circuit coupled to the selector to provide a feedback signal from the selected first signal to the resistor network, the resistor network generating a second plurality of signals; and

wherein the selector selects a second signal from the second plurality of signals based on the second half of the digital word, the second signal corresponding to the analog quantity.

12. The apparatus of claim 11 wherein the selector comprises:

a decoder coupled to the input multiplexer to decode the first half of the digital word to generate a first control word;

a switching array coupled to the decoder to transfer the first plurality of signals according to the first control word and to combine the transferred first plurality of signals to generate the first signal.

13. The apparatus of claim 11 wherein the sample-and-hold circuit:

samples the selected first signal in a first clock period;

holds the sampled first signal in a second clock period; and

provides the sampled and held first signal to the single resistor network.

14. The apparatus of claim 11 wherein the decoder decodes the second half of the digital word to generate a second control word to the switching array, the switching array transferring the second plurality of signals according to the second control word and combining the transferred second plurality of signals to generate the second signal.

15. An apparatus to convert a digital word to an analog quantity, the apparatus comprising:

a resistor network to generate a first plurality of signals;

an input multiplexer coupled to receive the digital word to provide a first half and a second half of the digital word;

a selector coupled to the resistor network to select a first top and bottom signals from the first plurality of signals based on the first half of the digital word;

top and bottom sample-and-hold circuits coupled to the selector to provide top and bottom feedback signals from the selected first top and bottom signals to the resistor network, the resistor network generating a second plurality of signals; and

wherein the selector selects second top and bottom signals from the second plurality of signals based on the second half of the digital word, one of the second top and bottom signals corresponding to the analog quantity.

16. The apparatus of claim 15 wherein the selector comprises:

a decoder coupled to the input multiplexer to decode the first half of the digital word to generate a first control word; and

a switching array coupled to the decoder to transfer the plurality of signals according to the first control word and to combine the transferred signals to generate the first top and bottom signals.

17. The apparatus of claim 15 wherein the top and bottom sample-and-hold circuits:

sample the selected first top and bottom signals in a first clock period;

hold the sampled first top and bottom signals in a second clock period; and

provide the sampled and held first top and bottom signals to the resistor network.

18. The apparatus of claim 17 further comprising:

top and bottom drive circuits coupled to the top and bottom sample-and-hold circuits to generate top and bottom feedback signals based on a select signal in the second clock period, the top and bottom feedback signals being coupled to the resistor network to generate the second plurality of signals.

19. The apparatus of claim 18 wherein

the top and bottom sampled-and-hold circuits are coupled to the top and bottom drive circuits, respectively, when the select signal is at a first logic level;

and

the top and bottom sampled-and-hold circuits are coupled to the bottom and top drive circuits, respectively, when the select signal is at a second logic level.

20. The apparatus of claim 15 wherein the decoder decodes the second half of the digital word to generate a second control word to the switching array, the switching array transferring the second plurality of signals according to the second control word and combining the transferred second plurality of signals to generate the second top and bottom signals.