Five transistor SRAM cell for small micromirror elements

• US 6,191,883 B1
• Filed: 12/23/1999
• Issued: 02/20/2001
• Est. Priority Date: 12/30/1998
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Miller, Rodney D., Huffman, James D.
• Primary Examiner(s): Ben, Loha
• Application Number:
  US09/470,719
• Time in Patent Office: 425 Days
• Field of Search: 359/290, 359/291, 359/295, 359/223, 359/224, 359/248, 359/245, 342/21, 342/27, 345/84, 345/85, 324/765, 324/763, 395/281, 395/555
• US Class Current: 359/291
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger

Abstract

An improved memory cell (300) for use in applications, such as micromirror arrays, in which little space is available and a slow read-back cycle is tolerated. The memory (300) comprises a first input/output node (314) connected to the input of a first inverter and to the output of a second inverter. The first inverter is comprised of two transistors (304, 306) and drives a signal to a second input/output node (316). The input of the second inverter is connected to the second input/output node (316). When used to drive a typical micromirror cell, the address electrode of the micromirror cell are electrically connected to the first input/output node (314) and the second input/output node (316).

Claims

1. A micromirror device comprising:

a semiconductor substrate;

at least one memory cell formed in said substrate, said memory cell comprising;

a first input/output node;

a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and

a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node;

at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes;

at least one deflectable member supported by said semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.

2. The micromirror device of claim 1, further comprising:

a bitline; and

a write transistor connecting said bitline to said first input/output node.

3. The micromirror device of claim 2, wherein a 7.5 volt write signal is used to enable said write transistor.

4. The micromirror device of claim 2, further comprising:

a pre-charge capacitor electrically connected to said bitline.

5. The micromirror device of claim 4, further comprising:

a pair of pre-charge transistors, each of said pre-charge transistors connecting said bitline to a supply voltage.

6. The micromirror device of claim 1, each of said first and second inverters comprising two transistors.

7. A memory cell comprising:

a first input/output node;

a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and

a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node;

at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes;

at least one deflectable member supported by a semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.

8. The memory cell of claim 7, further comprising:

a bitline; and

a write transistor connecting said bitline to said first input/output node.

9. The memory cell of claim 8, wherein a 7.5 volt write signal is used to enable said write transistor.

10. The memory cell of claim 8, further comprising:

a pre-charge capacitor electrically connected to said bitline.

11. The micromirror device of claim 10, further comprising:

a pair of pre-charge transistors, each of said pre-charge transistors connecting said bitline to a supply voltage.

12. A image projection system comprising:

a light source for providing a beam of light along a light path;

a micromirror device on said light path for selectively reflecting portions of said beam of light along a second light path in response to image data signals;

a controller for providing image data signals to said micromirror device; and

a projection lens on said second light path for focusing said selectively reflected light onto an image plane;

said micromirror device comprising;

a semiconductor substrate;

at least one memory cell fabricated on said semiconductor substrate, said memory cell comprising;

a first input/output node;

a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and

a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node;

at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes;

at least one deflectable member supported by said semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.