Five transistor SRAM cell for small micromirror elements
First Claim
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1. A micromirror device comprising:
- a semiconductor substrate;
at least one memory cell formed in said substrate, said memory cell comprising;
a first input/output node;
a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and
a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node;
at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes;
at least one deflectable member supported by said semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.
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Abstract
An improved memory cell (300) for use in applications, such as micromirror arrays, in which little space is available and a slow read-back cycle is tolerated. The memory (300) comprises a first input/output node (314) connected to the input of a first inverter and to the output of a second inverter. The first inverter is comprised of two transistors (304, 306) and drives a signal to a second input/output node (316). The input of the second inverter is connected to the second input/output node (316). When used to drive a typical micromirror cell, the address electrode of the micromirror cell are electrically connected to the first input/output node (314) and the second input/output node (316).
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Citations
12 Claims
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1. A micromirror device comprising:
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a semiconductor substrate;
at least one memory cell formed in said substrate, said memory cell comprising;
a first input/output node;
a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and
a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node;
at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes;
at least one deflectable member supported by said semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member. - View Dependent Claims (2, 3, 4, 5, 6)
a bitline; and
a write transistor connecting said bitline to said first input/output node.
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3. The micromirror device of claim 2, wherein a 7.5 volt write signal is used to enable said write transistor.
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4. The micromirror device of claim 2, further comprising:
- a pre-charge capacitor electrically connected to said bitline.
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5. The micromirror device of claim 4, further comprising:
a pair of pre-charge transistors, each of said pre-charge transistors connecting said bitline to a supply voltage.
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6. The micromirror device of claim 1, each of said first and second inverters comprising two transistors.
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7. A memory cell comprising:
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a first input/output node;
a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and
a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node;
at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes;
at least one deflectable member supported by a semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member. - View Dependent Claims (8, 9, 10, 11)
a bitline; and
a write transistor connecting said bitline to said first input/output node.
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9. The memory cell of claim 8, wherein a 7.5 volt write signal is used to enable said write transistor.
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10. The memory cell of claim 8, further comprising:
a pre-charge capacitor electrically connected to said bitline.
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11. The micromirror device of claim 10, further comprising:
a pair of pre-charge transistors, each of said pre-charge transistors connecting said bitline to a supply voltage.
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12. A image projection system comprising:
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a light source for providing a beam of light along a light path;
a micromirror device on said light path for selectively reflecting portions of said beam of light along a second light path in response to image data signals;
a controller for providing image data signals to said micromirror device; and
a projection lens on said second light path for focusing said selectively reflected light onto an image plane;
said micromirror device comprising;
a semiconductor substrate;
at least one memory cell fabricated on said semiconductor substrate, said memory cell comprising;
a first input/output node;
a first inverter having an input and an output, said input of said first inverter electrically connected to said first input/output node, said output of said first inverter electrically connected to a second input/output node; and
a second inverter having an input and an output, said input of said second inverter electrically connected to said second input/output node, said output of said second inverter electrically connected to said first input/output node;
at least one address electrode, said at least one address electrode electrically connected to one of said first and second input/output nodes;
at least one deflectable member supported by said semiconductor substrate, said deflectable member operable to deflect when electrostatically attracted to said at least one address electrode by a voltage differential between said address electrode and said deflectable member.
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Specification