Non-volatile NAND type semiconductor memory device with stacked gate memory cells and a stacked gate select transistor

• US 6,191,975 B1
• Filed: 12/21/1999
• Issued: 02/20/2001
• Est. Priority Date: 12/22/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aritome, Seiichi, Shimizu, Kazuhiro, Satoh, Shinji
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/468,333
• Time in Patent Office: 427 Days
• Field of Search: 365/185.17, 365/185.01, 257/316, 257/326, 257/315
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

In the field of EEPROM, memory cell structures and operation methods have been required which are suitable for ultrahigh-integration and high-reliability EEPROMS with no danger of erroneous writing. To meet this requirement, in this invention, the gate of each of select gate cells located on the source line side and the bit line side of a NAND type memory cell array is formed of two layers of a charge storage layer and a control gate layer as with memory cells. The select gate cells are formed at the same time in the same process as memory cells. The ion implantation conditions for the cell channels are set so as to optimize the memory cell channel boost ratio. The optimization of the cutoff characteristic required of the select gate cells is performed by injection of charges into the charge storage layers of the select gate cells without owing to ion implantation. The memory and select gate cells are formed into the same shape. The charge storage layer is formed to self-align to an isolation trench.

Claims

1. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer each of which is of substantially the same dimension as that of the memory cells, and

writing data into the first and second select gate cells is performed prior to writing data into the memory cells.

2. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer each of which is of substantially the same dimension as that of the memory cells, and

writing data into the second select gate cell is performed prior to writing data into the first select gate cell.

3. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer each of which is of substantially the same dimension as that of the memory cells, and

a threshold voltage of the first select gate cell after writing data therein is lower than a threshold voltage of the second select gate cell after writing therein.

4. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer each of which is of substantially the same dimension as that of the memory cells, and

a plurality of the NAND cells constitutes a memory block, and writing data into the second select gate cells in at least the same column is performed at one time for all memory blocks each comprised of a plurality of the NAND cells.

5. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer each of which is of substantially the same dimension as that of the memory cells, and

writing data into the first and second select gate cells is performed using a write voltage that changes in a step-like manner from an initial voltage, and the written state is read at each step for write verification.

6. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell have a control gate layer and a charge storage layer, and

in a data write mode for writing data into the memory cell array, a memory cell located on the bit line side of a non-selected memory cell to be not written which memory cell is connected to the same word line as a selected memory cell to be written or the first select gate cell and a memory cell located on the source line side of the non-selected memory cell or the second select gate cell are turned off.

10. The non-volatile semiconductor memory device according to claim 6, wherein the control gate layer and the charge storage layer of each of the first and second select gate cells is of substantially the same dimension as that of the memory cells.

7. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND cells, each of the NAND memory cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer,

the memory cells and the first and second select gate cells are formed in each of a plurality of device regions defined by device isolation regions formed by filling isolation trenches extending along a direction of a semiconductor substrate with an insulating material,

the charge storage layer of each of the memory cells and the first and second select gate cells is formed above the device region to self-align to the device region with a first gate insulating film interposed therebetween,

the control gate layer of each of the memory cells and the first and second select gate cells is formed above the charge storage layer with a second gate insulating film interposed therebetween, the second gate insulating film covering a top and part of the sidewall of the charge storage layer, the charge storage layer is self-aligned to the isolation trenches, and has a lower portion contiguous to the device isolation region and an upper portion that is opposite to the control gate layer with the second gate insulating film interposed therebetween, and a height of the lower portion of the charge storage layer is substantially the same for the memory cells and the first and second select gate cells.

11. The non-volatile semiconductor memory device according to claim 7, wherein the control gate layer and the charge storage layer of each of the first and second select gate cells is of substantially the same dimension as that of the memory cells.

8. A non-volatile semiconductor memory device comprising:

a memory cell array including NAND memory cells, each of the NAND memory cells having a plurality of memory cells and at least one of a first select gate cell and a second select gate cell, the plurality of memory cells being connected in series to form a NAND string, the first select gate cell being connected between a bit line and the memory cell nearest to the bit line, the second select gate cell being connected between a source line and the memory cell nearest to the source line, and each of the memory cells having a charge storage layer and a control gate layer, wherein

each of the first select gate cell and the second select gate cell has a control gate layer and a charge storage layer,

a plurality of transfer transistors are provided, each of which is connected in parallel with a corresponding respective one of the memory cells and the first and second select gate cells, and

a threshold voltage of the transfer transistors is substantially equal to that of at least one of the first and second select gate cells.

9. The non-volatile memory device according to claim 8, wherein

the memory cells and the first and second select gate cells are formed in each of a plurality of device regions defined by device isolation regions formed by filling isolation trenches extending along a direction of a semiconductor substrate with an insulating material,

the charge storage layer of each of the memory cells and the first and second select gate cells is formed above the device region to self-align to the device region with a first gate insulating film interposed therebetween,

the control gate layer of each of the memory cells and the first and second select gate cells is formed above the charge storage layer and the device region with a second and a third gate insulating film interposed therebetween, the second gate insulating film covering a top and sidewall of the charge storage layer and the third gate insulating film covering the upper portion of the device region, the third gate insulating film being thicker than the first insulating film,

the charge storage layer is self-aligned to the isolation trenches, and

the transfer transistor has a MOS structure formed by the control gate layer and the upper portion of the device region opposite to each other with the third gate insulating film interposed therebetween.

12. The non-volatile semiconductor memory device according to claim 8, wherein the control gate layer and the charge storage layer of each of the first and second select gate cells is of substantially the same dimension as that of the memory cells.