Non-volatile semiconductor memory device
First Claim
1. A non-volatile semiconductor memory device comprising:
- bias voltage supplying circuit for supplying a predetermined bias voltage to a bit line by letting a current flow from a load circuit, in response to a first timing signal produced when an address of a memory cell is selected, to said memory cell to be connected to said bit line by a bit line selecting circuit in accordance with selection of said address and for generating a reading voltage at a point of connection with said load circuit by letting the current flow in accordance with an ON-state or OFF-state of said memory cell, a pre-charging circuit for letting a current flow to said bit line in response to a second timing signal produced in an early stage when said second timing signal is active; and
whereby said pre-charging circuit is operated to interrupt a current in a last stage when said second timing signal is active.
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Accused Products
Abstract
A non-volatile semiconductor memory device is provided which is capable of shortening time required for determining a reading voltage in its reading circuit and of improving a data reading speed. The non-volatile semiconductor memory device has a feedback-type bias circuit for letting currents to flow, in response to a first timing signal occurring when an address of a memory cell is selected from a load circuit to the memory cell to be connected to a bit line through a bit line decoder according to selection of the address and to be connected through a word line, causing a predetermined bias current to be supplied to the bit line and for letting a current to flow in accordance with an ON-state or OFF-state of the memory cell, causing a reading voltage to be produced at a connection point with the load circuit and a pre-charging circuit for letting currents to flow through the bit line in response to a second timing signal occurring in an early stage when the first timing signal is active and for interrupting currents flowing through the bit line in a last stage when the second timing signal is active.
32 Citations
15 Claims
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1. A non-volatile semiconductor memory device comprising:
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bias voltage supplying circuit for supplying a predetermined bias voltage to a bit line by letting a current flow from a load circuit, in response to a first timing signal produced when an address of a memory cell is selected, to said memory cell to be connected to said bit line by a bit line selecting circuit in accordance with selection of said address and for generating a reading voltage at a point of connection with said load circuit by letting the current flow in accordance with an ON-state or OFF-state of said memory cell, a pre-charging circuit for letting a current flow to said bit line in response to a second timing signal produced in an early stage when said second timing signal is active; and
whereby said pre-charging circuit is operated to interrupt a current in a last stage when said second timing signal is active. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification