Programmable logic device memory array circuit having combinable single-port memory arrays

• US 6,191,998 B1
• Filed: 12/01/1999
• Issued: 02/20/2001
• Est. Priority Date: 10/16/1997
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Reddy, Srinivas T., Lane, Christopher F., Mejia, Manuel
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US09/452,627
• Time in Patent Office: 447 Days
• Field of Search: 365/230.05, 365/189.08, 365/189.04
• US Class Current: 365/230.05
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable single-port memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations. When such a dual-port capability is not required, two single-port memory arrays are available to implement a desired logic design.

Claims

1. A programmable logic device comprising:

a plurality of programmable logic regions wherein the plurality of programmable logic regions are arranged in intersecting rows and columns;

a plurality of first combinable single-port memory arrays each having a plurality of rows and columns of memory cells for storing data;

a plurality of second combinable single-port memory arrays each associated with a respective one of the first combinable single-port memory arrays and each having a plurality of rows and columns of memory cells for storing data, wherein the first and second combinable single-port memory arrays are combinable to form a plurality of dual-port memory arrays and wherein the first and second combinable single-port memory arrays are arranged in intersecting rows and columns; and

a plurality of interconnects for routing signals between the programmable logic regions and the first and second combinable single-port memory arrays.

2. The programmable logic device defined in claim 1 wherein:

the first combinable single-port memory arrays each have a maximum data width;

the associated second combinable single-port memory arrays each have a maximum data width; and

the dual-port memory arrays formed from the first and second combinable single-port memory arrays each have a maximum data width greater than the maximum data width of either the first combinable single-port memory arrays or the second single-port memory arrays taken alone.

3. The programmable logic device defined in claim 1 wherein the first and second combinable single-port memory arrays are combinable using circuitry from respective ones of the first combinable single-port memory arrays to perform writing operations and using circuitry from respective ones of the second combinable single-port memory arrays that are associated with each of the first combinable single-port memory arrays to perform concurrent reading operations.

4. The programmable logic device defined in claim 1 wherein the first and second combinable single-port memory arrays comprise variable depth and width memory arrays.

5. The programmable logic device defined in claim 1 wherein at least one of the first combinable single-port memory arrays and one of the second combinable single-port memory arrays are in each of the rows.

6. The programmable logic device defined in claim 1 wherein the first and second combinable single-port memory arrays further comprise:

first input multiplexing circuitry for distributing data signals to respective ones of the first combinable single-port memory arrays; and

second input multiplexing circuitry for distributing data signals to respective ones of the second combinable single-port memory arrays.

7. The programmable logic device defined in claim 1 wherein the first and second combinable single-port memory arrays further comprise:

first input registers for registering data to be written to respective ones of the first combinable single-port memory arrays; and

second input registers for registering data to be written to respective ones of the second combinable single-port memory arrays.

8. The programmable logic device defined in claim 1 wherein the first and second combinable single-port memory arrays further comprise:

first output registers for registering data that has been read from respective ones of the first combinable single-port memory arrays; and

second output registers for registering data that has been read from respective ones of the second combinable single-port memory arrays.

9. The programmable logic device defined in claim 1 wherein the first memory arrays further comprise:

a write column select line associated with each column of each memory array for controlling the transfer of data into the cells of that column; and

a read column select line associated with each column of each memory array for controlling the transfer of data from the cells in that column, wherein the write column select line and the read column select line operate independently.

10. The programmable logic device defined in claim 1 wherein the second memory arrays further comprise:

a write column select line associated with each column of each memory array for controlling the transfer of data into the cells of that column; and

a read column select line associated with each column of each memory array for controlling the transfer of data from the cells in that column, wherein the write column select line and the read column select line operate independently.

11. The programmable logic device defined in claim 1 wherein:

the first combinable single-port memory arrays further comprise a first write column select line associated with each column of each first combinable memory array for controlling the transfer of data into the cells of that column and a first read column select line associated with each column of each first memory array for controlling the transfer of data from the cells in that column, wherein the first write column select line and the first read select line operate independently; and

the second combinable single-port memory arrays further comprise a second write column select line associated with each column of each first memory array for controlling the transfer of data into the cells of that column and a second read column select line associated with each column of each second memory array for controlling the transfer of data from the cells in that column, wherein the second write column select line and the second read select line operate independently.

12. The programmable logic device defined in claim 1 wherein:

the first and second combinable single-port memory arrays are combinable using circuitry from respective ones of the first combinable single-port memory arrays to perform writing operations and using circuitry from respective ones of the second combinable single-port memory arrays that are associated with each of the first combinable single-port memory arrays to perform concurrent reading operations; and

the circuitry from each of the first combinable single-port memory arrays that is used to perform dual-port memory array writing operations comprises variable depth and width writing circuitry for performing write operations with selectable-size data words by addressing selected write locations within the rows and columns of cells in the first combinable single-port memory array and by writing data words into those write locations; and

the circuitry from each of the second combinable single-port memory arrays that is used to perform dual-port memory array reading operations comprises variable depth and width reading circuitry for performing read operations with selectable-size data words concurrently with the write operations performed by the variable depth and width writing circuitry by addressing selected read locations within the rows and columns of cells in the second combinable single-port memory array and by reading data words from those read locations.