Method and apparatus for configuring the pinout of an integrated circuit

• US 6,192,431 B1
• Filed: 12/31/1997
• Issued: 02/20/2001
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cheng, Christopher, Dabral, Sanjay, Sampath, Dilip K.
• Primary Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US09/001,550
• Time in Patent Office: 1,147 Days
• Field of Search: 710/8, 710/62-74
• US Class Current: 710/62
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/181 associated with surface mounted components
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/10545 Related components mounted on both sides of the PCB
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A method and apparatus for configuring the pinout of an integrated circuit. An integrated circuit includes an input/output structure including an input/output port. The input/output structure communicates a first signal in a first configuration and a second signal in a second configuration. The first and second signals are parallel signals of a bus.

Claims

1. An integrated circuit comprising:

a first input/output (IO) port to communicate a first signal in a first configuration and a second signal in a second configuration, the first and second signals being parallel signals of a bus;

a first multiplexer coupled to the first IO port;

a configuration IO port, the configuration IO port being an electrical connector disposed on a package of the integrated circuit; and

a configuration signal line coupled between the first multiplexer and the configuration IO port to select between the first configuration and the second configuration.

2. The integrated circuit of claim 1, wherein the first IO port is connected to an input of the first multiplexer.

3. The integrated circuit of claim 1, wherein the first IO port is connected to an output of the first multiplexer.

4. The integrated circuit of claim 1, further comprising a second IO port to communicate the second signal in the first configuration and the first signal in the second configuration.

5. The integrated circuit of claim 4, further comprising a second multiplexer connected to the second IO port and to the configuration signal line.

6. A processor comprising:

a parallel signal bus having a first signal line to communicate a predetermined first bit position of the bus and a second signal line to communicate a predetermined second bit position of the bus;

a first input/output (IO) port selectively connected to the first signal line in a first configuration and to the second signal line in a second configuration;

a second IO port selectively connected to the second signal line in the first configuration and to the first signal line in the second configuration; and

a configuration IO port to select between the first configuration and the second configuration, the configuration IO port being an electrical connector disposed on a package of the processor.

7. The processor of claim 6, further comprising:

a first multiplexer having an input connected to the first IO port, another input connected to the second IO port, and an output connected to the first signal line; and

a second multiplexer having an input connected to the first IO port, another input connected to the second IO port, and an output connected to the second signal line.

8. The processor of claim 6, further comprising:

a first multiplexer having an input connected to the first signal line, another input connected to the second signal line, and an output connected to the first IO port; and

a second multiplexer having an input connected to the first signal line, another input connected to the second signal line, and an output connected to the second IO port.

9. The processor of claim 6, further comprising a configuration IO port to select between the first configuration and the second configuration.

10. An electronic component comprising:

a printed circuit board (PCB);

a power plane disposed in the PCB;

a ground plane disposed in the PCB;

a first integrated circuit (IC) connected to the PCB, the first IC having a first pinout configuration;

a first electrical interconnect connected to a configuration input/output port of the first IC at one end and to the power plane at another end to place the first IC in the first pinout configuration, the configuration input/output port of the first IC being an electrical connector disposed on a package of the IC;

a second IC connected to the PCB, the second IC being identical to the first IC and having a second pinout configuration that is a mirror image of at least a portion of the first pinout configuration; and

a second electrical interconnect connected to a configuration input/output port of the second IC at one end and to the ground plane at another end to place the second IC in the second pinout configuration, the configuration input/output port of the second IC being an electrical connector disposed on a package of the IC.

11. The electronic component of claim 10, wherein the portion of the first pinout configuration is of a bus of the first and second ICs.

12. The electronic component of claim 10, wherein the first and second ICs are processors.

13. The electronic component of claim 10, wherein the first and second ICs are cache memory devices.

14. A method of coupling a bus in a first integrated circuit (IC) to a bus in a second IC that is identical to the first IC, the method comprising:

configuring the first IC to have a bus pinout in a first configuration using a first configuration input/output port of the first IC, the first configuration input/output port being an electrical connector disposed on a package of the first IC; and

configuring the second IC to have a bus pinout in a second configuration that is inverted from the first configuration using a second configuration input/output port of the second IC, the second configuration input/output port being an electrical connector disposed on a package of the second IC.

15. The method of claim 14, further comprising the step of electrically coupling the bus in the first IC to the bus in the second IC.

16. The method of claim 14, wherein the step of configuring the first IC includes the step of electrically coupling the first configuration input/output port of the first IC to a power plane and the step of configuring the second IC includes the step of electrically coupling the second configuration input/output port of the second IC to a ground plane.