Method for coupling to semiconductor device in an integrated circuit having edge-defined, sub-lithographic conductors

• US 6,194,262 B1
• Filed: 03/29/2000
• Issued: 02/27/2001
• Est. Priority Date: 04/25/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/537,602
• Time in Patent Office: 335 Days
• Field of Search: 438/238, 438/239, 438/253-256, 438/381, 438/346-399
• US Class Current: 438/253
• CPC Class Codes: H01L 28/91 made by depositing layers, e.g. by depositing alternating conductive and insulating layers
• CPC Class Codes: H10B 12/312 with a bit line higher than the capacitor
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: Y10S 257/905 Plural dram cells share common contact or common trench
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

An integrated circuit comprising stacked capacitor memory cells having sub-lithographic, edge-defined word lines and a method for forming such an integrated circuit. The method forms conductors adjacent to sub-lithographic word lines in order to couple a stacked capacitor to the access transistor of the memory cell. The conductors are bounded by the word lines. The bit line and capacitor are formed with a single mask image in such a manner as to self-align the bit line and the capacitor and to maximize the capacitance of the memory device. The method may be used to couple any suitable circuit element to a semiconductor device in an integrated circuit having edge-defined, sub-lithographic word lines.

Claims

1. An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising:

a semiconductor device formed in a semiconductor substrate;

a first conductor formed outwardly from the first semiconductor device, the first conductor having a width less than the minimum lithographic dimension;

a second conductor formed outwardly from the first semiconductor device, the second conductor adjacent to the first conductor; and

a circuit element coupled to the semiconductor device by the second conductor.

2. The integrated circuit according to claim 1 further comprising a bit line formed outwardly from the semiconductor device and wherein the circuit element is a storage capacitor, the semiconductor device is a transistor for coupling the bit line to the storage capacitor through the second conductor, and the first conductor is a word line for activating the transistor.

3. The integrated circuit according to claim 2 wherein the second conductor and the bit line are bounded by the word line.

4. The integrated circuit device according to claim 2 wherein the bit line and the storage capacitor are formed using a single mask image.

5. A memory device formed by a lithographic process having a minimum lithographic dimension, comprising:

a plurality of transistors formed in a semiconductor substrate, the transistors having a shared drain, each the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate;

a plurality of word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to the gate of a different transistor for activating the transistor;

a bit line and a plurality of conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the conductors adjacent to the word lines; and

a plurality of storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor.

6. The memory device according to claim 5 wherein the conductors and the bit line are bounded by the word lines.

7. The memory device according to claim 5 wherein the bit line and the storage capacitors are formed using a single mask image.

8. A pair of memory cells for an integrated memory device formed using a lithographic process having a minimum lithographic dimension, comprising:

two transistors formed in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate;

two word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors;

a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistors, the bit line and the two conductors adjacent to the word line; and

two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistors by one of the conductors.

9. The pair of memory cells according to claim 8 wherein the conductors and the bit line are bounded by the word lines.

10. The pair of memory cells according to claim 8 wherein the bit line and the storage capacitors are formed by using a single mask image.

11. A semiconductor memory device formed using a lithographic process having a minimum lithographic dimension, comprising:

a transistor formed in a semiconductor substrate;

a word line formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension, wherein the word line is used to activate the transistor;

a bit line formed outwardly from the transistor which is coupled to the transistor, wherein the bit line is adjacent to the word line;

a conductor formed outwardly from the transistor which is coupled to the transistor, wherein the conductor is adjacent to the word line; and

a storage capacitor formed outwardly from the bit line and the conductor, wherein the storage capacitor is coupled to the transistor by the conductor.

12. The semiconductor memory device of claim 11, wherein the conductor and the bit line are bounded by the word line.

13. The semiconductor memory device of claim 11, wherein the bit line is self aligned with the storage capacitor using a single mask image.

14. A method for forming an integrated circuit using a lithographic process having a minimum lithographic dimension, comprising the steps of:

forming a semiconductor device in a semiconductor substrated;

forming a first conductor outwardly from the semiconductor device, the first conductor having a width less than the minimum lithographic dimension;

forming a second conductor outwardly from the semiconductor device, the second conductor adjacent to and bounded by the first conductor; and

coupling a storage capacitor to the semiconductor device by the second conductor, wherein the second conductor is self-aligned with the storage capacitor by using a single mask image.

15. The method of claim 14, wherein forming a semiconductor device comprises forming a transistor for accessing the storage capacitor.

16. The method of claim 15, wherein forming a first conductor comprises forming a word line for activating the transistor.

17. A method of fabricating two memory cells having a shared bit line using a lithographic process having a minimum lithographic dimension, comprising:

forming two transistors in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate extending outwardly from the semiconductor substrate;

forming two word lines outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, one word line connected to a gate of one of the two transistors and one word line connected to the other for activating the transistor;

forming a bit line and two conductors outwardly from the transistors that couple to the transistor, the bit line coupled to the shared drain of the transistors, one conductor coupled to a source of one of the two transistors and one conductor coupled to a source of the other transistor, the bit line and the conductors adjacent to and bounded by the word lines; and

forming two storage capacitors outwardly from the bit line and the conductors, one storage capacitor coupled to a source of one of the two transistors by one of the conductors and one storage capacitor coupled to a source of the other transistor by the other conductor, wherein the bit line is self-aligned with the one storage capacitor by using a single mask image.

18. An integrated circuit formed using a lithographic process having a minimum lithographic dimension, comprising:

a transistor formed in a semiconductor substrate;

a bit line formed outwardly from the transistor;

a word line for activating the transistor formed outwardly from the transistor, the word line having a width less than the minimum lithographic dimension;

a first conductor formed outwardly from the transistor, the second conductor adjacent to the word line, wherein the first conductor and the bit line are bounded by the word line; and

a storage capacitor coupled to the transistor by the word line, wherein the transistor couples the bit line to the storage capacitor through the first conductor and wherein the bit line and the storage capacitor are formed using a single mask image.

19. A memory device formed by a lithographic process having a minimum lithographic dimension, comprising:

a plurality of transistors formed in a semiconductor substrate, the transistors having a shared drain, each the transistors having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate;

a plurality of word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to the gate of a different transistor for activating the transistor;

a bit line and a plurality of conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistor, the bit line and the conductors adjacent to the word lines;

a plurality of storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistor by a different conductor; and

wherein the conductors and the bit line are bounded by the word lines and the bit line and the storage capacitors are formed using a single mask image.

20. A pair of memory cells for an integrated memory device formed using a lithographic process having a minimum lithographic dimension, comprising:

two transistors formed in a semiconductor substrate, the transistors having a shared drain, each transistor having a gate and a source, the gate of each transistor extending outwardly from the semiconductor substrate;

two word lines formed outwardly from the transistors, each word line having a width less than the minimum lithographic dimension, each word line connected to a gate of a different transistor, the word lines for activating the transistors;

a bit line and two conductors formed outwardly from the transistors, the bit line connected to the shared drain of the transistors, each conductor connected to the source of a different transistors, the bit line and the two conductors adjacent to the word line and wherein the conductors and the bit line are bounded by the word lines; and

two storage capacitors formed outwardly from the bit line and the conductors, each storage capacitor coupled a source of a different transistors by one of the conductors, wherein the bit line and the storage capacitors are formed by using a single mask image.