MOSgated trench type power semiconductor with silicon carbide substrate and increased gate breakdown voltage and reduced on-resistance

• US 6,194,741 B1
• Filed: 11/03/1998
• Issued: 02/27/2001
• Est. Priority Date: 11/03/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Kinzer, Daniel M., Sridevan, Srikant
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US09/185,110
• Time in Patent Office: 847 Days
• Field of Search: 257/329, 257/330, 257/77
• US Class Current: 257/77
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A MOSgated trench type power semiconductor device is formed in 4H silicon carbide with the low resistivity direction of the silicon carbide being the direction of current flow in the device drift region. A P type diffusion at the bottom of the U shaped grooves in N− silicon carbide helps prevent breakdown of the gate oxide at the trench bottom edges. The gate oxide may be shaped to increase its thickness at the bottom edges and has a trapezoidal or spherical curvature. The devices may be implemented as depletion mode devices.

Claims

1. A power MOSgated device comprising a substrate of silicon carbide having an upper surface;

a plurality of spaced U shaped grooves formed into the surface of said substrate to a first depth;

said substrate having a channel region of one of the conductivity types and which has a second depth beneath said upper surface which is less than said first depth and having a source region of the other of the conductivity types and which has a third depth beneath said upper surface which is less than said second depth;

a gate insulation layer disposed within and along the walls of said grooves;

a conductive polysilicon gate filling said grooves and spaced from the walls of said grooves by said gate insulation layer;

a source contact connected to said channel region and to said source region;

a drain contact connected to said substrate at a location remote from said channel region; and

a gate contact connected to said polysilicon gates;

said silicon carbide consisting of a polycrystalline silicon carbide having a reduced resistivity in the direction of conduction of current in a direction parallel to the vertical walls of said grooves as compared to a resistivity in the direction of conduction of current in a direction perpendicular to the vertical walls of said grooves; and

a diffusion of said one conductivity type extending from and beneath the bottoms of each of said grooves to reduce the tendency of dielectric breakdown of said gate insulation at the bottom of said grooves.

2. The device of claim 1 in which said gate insulation comprises silicon dioxide.

3. The device of claim 1 in which said one conductivity type is P.

4. The device of claim 2 in which said one conductivity types is P.

5. A power MOSgated device comprising a substrate of silicon carbide having an upper surface;

a plurality of spaced U shaped grooves formed into the surface of said substrate to a first depth;

said substrate having a channel region of one of the conductivity types and which has a second depth beneath said upper surface which is less than said first depth and having a source region of the other of the conductivity types and which has a third depth beneath said upper surface which is less than said second depth;

a gate insulation layer disposed within and along the walls of said grooves;

a conductive polysilicon gate filling said grooves and spaced from the walls of said grooves by said gate insulation layer;

a source contact connected to said channel region and to said source region;

a drain contact connected to said substrate at a location remote from said channel region; and

a gate contact connected to said polysilicon gates; and

a diffusion of said one conductivity type extending from and beneath the bottoms of each of said grooves to reduce the tendency of dielectric breakdown of said gate insulation at the bottom of said grooves.