VCO-mixer structure

• US 6,194,947 B1
• Filed: 07/24/1998
• Issued: 02/27/2001
• Est. Priority Date: 07/24/1998
• Status: Expired due to Term

• Current Assignee: GCT Semiconductor Incorporated
• Original Assignee: Hitachi Communication Technologies Limited (Hitachi, Ltd.)
• Inventors: Jeong, Deog-Kyoon, Lee, Kyeongho
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US09/121,863
• Time in Patent Office: 949 Days
• Field of Search: 327/113, 327/116, 327/359, 327/357, 455/326, 455/333
• US Class Current: 327/359
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03H 11/22 providing two or more phase shifted output signals, e.g. n-phase output
• CPC Class Codes: H03H 2011/0494 Complex filters
• CPC Class Codes: H03K 9/00 Demodulating pulses which have been modulated with a continuously-variable signal
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/1974 for fractional frequency division
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04B 1/403 using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency

Abstract

A VCO-mixer structure in accordance with the present invention includes a multi-phase VCO and a multi-phase mixer. The VCO includes a plurality of differential delay cells and the mixer includes a differential amplifying circuit and a combining circuit. The differential amplifying circuit of the multi-phase mixer includes two load resistors coupled to two differential amplifiers, respectively. The combining circuit includes bias transistors, first combining unit and second combining unit coupled to the bias transistors, respectively, and a current source coupled to the first and second combining units. The first combining unit includes a plurality of transistor units, and the second combining unit includes a second plurality of transistor units. Preferably, each of the plurality of transistor units includes a plurality of serially connected transistors, wherein the serially connected transistors are coupled in parallel with the serially connected transistors of the plurality of transistor units.

Claims

1. A circuit comprising:

a clock generator receiving a reference signal having a reference frequency that generates a plurality of first clock signals having different phases, each first clock signal having a first frequency which is less than said reference frequency; and

a mixer coupled to said clock generator for receiving the plurality of first clock signals to generate a plurality of local oscillator signals therein having a higher second frequency, wherein said mixer multiplies the plurality of local oscillator signals with input signals to provide output signals at output terminals.

2. The circuit of claim 1, wherein said clock generator includes a plurality of delay cells coupled in series for providing the plurality of first clock signals having different phases.

3. The circuit of claim 1, wherein said mixer includes:

a differential amplifying circuit for receiving the input signals and providing the output signals; and

a combining circuit coupled to the differential amplifying circuit for receiving the plurality of first clock signals from said clock generator and outputting the local oscillator signals.

4. The circuit of claim 3, wherein said differential amplifying circuit includes:

a first load resistor coupled for receiving a first potential; and

a first differential amplifier coupled to said first load resistor and the combining circuit.

5. The circuit of claim 4, wherein said differential amplifying circuit further comprises:

a second load resistor coupled for receiving the first potential; and

a second differential amplifier coupled to said second load resistor and the combining circuit.

6. The circuit of claim 3, wherein said combining circuit comprises:

a first combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding first local oscillator signal;

a second combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding second local oscillator signal; and

a current source coupled to said first and second combining units and coupled for receiving a second potential.

7. The circuit of claim 6, wherein the combining circuit further comprises first and second bias transistors respectively coupled between said first and second combining units and the differential amplifying circuit.

8. The circuit of claim 6, wherein each of said first and second combining units comprises a plurality of transistor units coupled to each other in parallel.

9. The circuit of claim 8, wherein each of said plurality of transistor units comprises a plurality of transistors coupled in series.

10. The circuit of claim 3, wherein the combining circuit combines the plurality of first clock signals to generate the plurality of local oscillator signals having the second frequency substantially the same as the reference frequency and, wherein the input signals have the reference frequency and the output signals are baseband.

11. The circuit of claim 10, wherein the combining circuit includes a plurality of transistor units coupled to each other in parallel, each transistor unit receiving at least one of the plurality of first clock signals as a respective control signal.

12. The circuit of claim 11, wherein each of the plurality of transistor units coupled in parallel includes a plurality of transistors coupled in series.

13. The circuit of claim 12, wherein each of the plurality of transistors receives a different one of the plurality of first clock signals as its respective control signals.

14. A circuit comprising:

a clock generator receiving a reference signal having a reference frequency that generates a plurality of first clock signals having N different phases, N being an integer greater than one, each first clock signal having a first frequency substantially equal to double a second frequency divided by N; and

a mixer coupled to the clock generator, that receives the plurality of first clock signals to generate at least one local oscillator signal therein having the second frequency, wherein the mixer multiplies the at least one local oscillator signal with input signals to provide output signals at output terminals.

15. The circuit of claim 14, wherein said mixer includes:

a differential amplifying circuit for receiving the input signals, said at least one local oscillator signal and providing the output signals; and

a combining circuit coupled to the differential amplifying circuit for receiving the plurality of first clock signals from said clock generator.

16. The circuit of claim 15, wherein the combining circuit combines the plurality of first clock signals to generate the at least one local oscillator signal having the second frequency greater than 1 GHz.

17. The circuit of claim 16, wherein the combining circuit includes a plurality of transistor units coupled to each other in parallel, each transistor unit receiving at least one of the plurality of first clock signals as a respective control signal.

18. The circuit of claim 17, wherein each of the plurality of transistor units coupled in parallel includes a plurality of transistors coupled in series.

19. The circuit of claim 18, wherein each of the plurality of transistors receives a corresponding one of the plurality of first clock signals as its respective control signals.

20. The circuit of claim 15, wherein said combining circuit comprises:

a first combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding first local oscillator signal;

a second combining unit for receiving corresponding first clock signals and coupled to said differential amplifying circuit to output a corresponding second local oscillator signal; and

a current source coupled to said first and second combining units and coupled for receiving a second potential, wherein the input signals have the reference frequency and the output signals are baseband.