Driver circuit for high speed data

• US 6,194,949 B1
• Filed: 03/04/1998
• Issued: 02/27/2001
• Est. Priority Date: 03/04/1998
• Status: Expired due to Term

• Current Assignee: RPX Clearinghouse LLC (RPX Corporation)
• Original Assignee: Nortel Networks Limited (Nortel Networks Corporation)
• Inventors: Hogeboom, John Gordon
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): ENGLUND, TERRY LEE
• Application Number:
  US09/034,905
• Time in Patent Office: 1,091 Days
• Field of Search: 326/17, 326/26, 326/27, 326/56, 326/57, 326/58, 326/83, 326/86, 327/333, 327/389, 327/391, 327/108, 327/374, 327/543, 327/541, 327/214, 327/52, 330/9, 330/51, 330/253, 330/258
• US Class Current: 327/391
• CPC Class Codes: H03K 19/018528 with at least one differential stage
• CPC Class Codes: H03K 19/09429 one of the states being the high impedance or floating state
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end

Abstract

A CMOS driver circuit for high-speed data transmission has a complementary differential switch formed by four transistors, a bias cell containing current mirrors controlled by a reference current, two drive-current limiting devices for limiting the drive current to a required value via the bias cell, a current-shunting switch, and buffers which drive each of the gate nodes of the switches. CMOS transistors used in these buffers are limited in size to limit the rate at which they operate the switches and to limit the rate at which current is steered from one side of the differential switch to the other. One supply side of each of these buffers is connected to one of the current-limited supply nodes of the main output switches, thus greatly reducing variations in switching rate. The CMOS devices have sizes optimized to achieve both the required switching speed and minimized sensitivity to variations affecting switching speed.

Claims

1. A driver circuit for transmission of data signals on a channel, said driver circuit comprising:

first and second buffer units for receiving data signals to be transmitted over the channel, each of said first and second buffer units including a first power supply side and a second power supply side;

a differential switch responsive to said data signals, said differential switch being driven by positive and negative drive-currents, said differential switch including;

a) a first switch coupled to said first buffer unit, said first buffer unit supplying said data signals to said first switch; and

b) a second switch coupled to said second buffer unit, said second buffer unit supplying said data signals to said second switch;

a pair of complementary output terminals coupled to said differential switch for releasing said data signals into the channel;

first and second drive-current limiting devices for limiting respective ones of said positive and negative drive-currents to a required value, said first drive-current limiting device being connected to said first switch via a first current-limited node, said second drive-current limiting device being connected to said second switch via a second current-limited node, one of said first and second power supply sides of said first buffer unit being coupled to said first current-limited node, one of said first and second power supply sides of said second buffer unit being coupled to said second current-limited node;

a bias cell connected to said first and second drive-current limiting devices for biasing said first and second drive-current limiting devices to the required value; and

a current-shunting switch operative to switch said positive and negative drive-currents such that said positive and negative drive-currents bypass said complementary output terminals.

2. A driver circuit as recited in claim 1, wherein said first switch includes a first pair of transistors and said second switch includes a second pair of transistors, said second pair of transistors being complementary to said first pair of transistors, said first and second pairs of transistors together forming two pairs of complementary transistors.

3. A driver circuit as recited in claim 1, wherein said bias cell includes an input for receiving a reference current, said bias cell including first and second current mirrors coupled to said input and being controlled by said reference current.

4. A driver circuit as recited in claim 2, wherein said first switch includes a first pair of gate nodes and said second switch includes a second pair of gate nodes, said second pair of gate nodes being complementary to said first pair of gate nodes, said first buffer unit including a first pair of buffers coupled to said first pair of gate nodes, said second buffer unit including a second pair of buffers coupled to said second pair of gate nodes.

5. A driver circuit as recited in claim 4, wherein said current-shunting switch includes a third pair of complementary transistors and a third pair of gate nodes, said driver circuit further comprising a third pair of buffers, each buffer of said third pair of buffers coupled to a respective one of said third pair of gate nodes.

6. A driver circuit as recited in claim 5, wherein a voltage at each of said current-limited nodes equals the sum of a voltage drop across the corresponding transistor of said differential switch and a signal amplitude at the corresponding output terminal.

7. A driver circuit as recited in claim 3, wherein

said first current mirror is operative:

a) to provide a first bias voltage to said first drive-current limiting device and

b) to provide a matching current of the reference current to said second current mirror, and

said second current mirror is operative;

a) to provide a second bias voltage to said second drive-current limiting device.

8. A driver circuit as recited in claim 7, wherein said first current mirror comprises:

a PMOS transistor operative to mirror said reference current, said PMOS transistor having a drain and a gate; and

a first amplifier including an input and an output, the input of said first amplifier being coupled to the drain of said PMOS transistor and the output of said first amplifier being coupled to said first drive-current limiting device for generating the first bias voltage.

9. A driver circuit as recited in claim 8, wherein the output of said first amplifier is further coupled to the gate of said PMOS transistor for providing feedback.

10. A driver circuit as recited in claim 8, wherein said second current mirror comprises:

an NMOS transistor coupled to said first current mirror to mirror said matching current, said NMOS transistor having a drain and a gate; and

a second amplifier having an input and an output, the input of said second amplifier being coupled to the drain of said NMOS transistor and the output of said second amplifier being coupled to said second drive-current-limiting device for generating the second bias voltage.

11. A driver circuit as recited in claim 10, wherein the output of said second amplifier is further coupled to the gate of said NMOS transistor for providing feedback.

12. A driver circuit as recited in claim 3, further comprising a third current-limited node, said reference current provided through a resistor connected to said third current-limited node.